mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-15 07:34:33 +00:00
6cdf2ea98e
gep to explicit addressing, we know that none of the intermediate
computation overflows.
This could use review: it seems that the shifts certainly wouldn't
overflow, but could the intermediate adds overflow if there is a
negative index?
Previously the testcase would instcombine to:
define i1 @test(i64 %i) {
%p1.idx.mask = and i64 %i, 4611686018427387903
%cmp = icmp eq i64 %p1.idx.mask, 1000
ret i1 %cmp
}
now we get:
define i1 @test(i64 %i) {
%cmp = icmp eq i64 %i, 1000
ret i1 %cmp
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125271 91177308-0d34-0410-b5e6-96231b3b80d8
237 lines
4.8 KiB
LLVM
237 lines
4.8 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout =
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"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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define i32 @test1(i32 %X) {
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entry:
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icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
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zext i1 %0 to i32 ; <i32>:1 [#uses=1]
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ret i32 %1
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; CHECK: @test1
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; CHECK: lshr i32 %X, 31
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; CHECK-NEXT: ret i32
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}
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define i32 @test2(i32 %X) {
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entry:
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icmp ult i32 %X, -2147483648 ; <i1>:0 [#uses=1]
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zext i1 %0 to i32 ; <i32>:1 [#uses=1]
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ret i32 %1
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; CHECK: @test2
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; CHECK: lshr i32 %X, 31
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; CHECK-NEXT: xor i32
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; CHECK-NEXT: ret i32
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}
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define i32 @test3(i32 %X) {
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entry:
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icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
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sext i1 %0 to i32 ; <i32>:1 [#uses=1]
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ret i32 %1
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; CHECK: @test3
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; CHECK: ashr i32 %X, 31
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; CHECK-NEXT: ret i32
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}
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define i32 @test4(i32 %X) {
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entry:
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icmp ult i32 %X, -2147483648 ; <i1>:0 [#uses=1]
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sext i1 %0 to i32 ; <i32>:1 [#uses=1]
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ret i32 %1
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; CHECK: @test4
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; CHECK: ashr i32 %X, 31
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; CHECK-NEXT: xor i32
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; CHECK-NEXT: ret i32
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}
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; PR4837
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define <2 x i1> @test5(<2 x i64> %x) {
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entry:
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%V = icmp eq <2 x i64> %x, undef
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ret <2 x i1> %V
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; CHECK: @test5
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; CHECK: ret <2 x i1> <i1 true, i1 true>
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}
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define i32 @test6(i32 %a, i32 %b) {
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%c = icmp sle i32 %a, -1
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%d = zext i1 %c to i32
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%e = sub i32 0, %d
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%f = and i32 %e, %b
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ret i32 %f
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; CHECK: @test6
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; CHECK-NEXT: ashr i32 %a, 31
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; CHECK-NEXT: %f = and i32 %e, %b
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; CHECK-NEXT: ret i32 %f
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}
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define i1 @test7(i32 %x) {
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entry:
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%a = add i32 %x, -1
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%b = icmp ult i32 %a, %x
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ret i1 %b
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; CHECK: @test7
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; CHECK: %b = icmp ne i32 %x, 0
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; CHECK: ret i1 %b
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}
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define i1 @test8(i32 %x){
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entry:
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%a = add i32 %x, -1
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%b = icmp eq i32 %a, %x
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ret i1 %b
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; CHECK: @test8
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; CHECK: ret i1 false
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}
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define i1 @test9(i32 %x) {
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entry:
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%a = add i32 %x, -2
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%b = icmp ugt i32 %x, %a
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ret i1 %b
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; CHECK: @test9
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; CHECK: icmp ugt i32 %x, 1
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; CHECK: ret i1 %b
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}
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define i1 @test10(i32 %x){
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entry:
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%a = add i32 %x, -1
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%b = icmp slt i32 %a, %x
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ret i1 %b
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; CHECK: @test10
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; CHECK: %b = icmp ne i32 %x, -2147483648
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; CHECK: ret i1 %b
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}
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define i1 @test11(i32 %x) {
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%a = add nsw i32 %x, 8
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%b = icmp slt i32 %x, %a
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ret i1 %b
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; CHECK: @test11
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; CHECK: ret i1 true
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}
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; PR6195
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define i1 @test12(i1 %A) {
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%S = select i1 %A, i64 -4294967295, i64 8589934591
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%B = icmp ne i64 bitcast (<2 x i32> <i32 1, i32 -1> to i64), %S
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ret i1 %B
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; CHECK: @test12
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; CHECK-NEXT: %B = select i1
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; CHECK-NEXT: ret i1 %B
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}
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; PR6481
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define i1 @test13(i8 %X) nounwind readnone {
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entry:
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%cmp = icmp slt i8 undef, %X
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ret i1 %cmp
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; CHECK: @test13
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; CHECK: ret i1 false
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}
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define i1 @test14(i8 %X) nounwind readnone {
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entry:
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%cmp = icmp slt i8 undef, -128
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ret i1 %cmp
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; CHECK: @test14
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; CHECK: ret i1 false
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}
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define i1 @test15() nounwind readnone {
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entry:
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%cmp = icmp eq i8 undef, -128
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ret i1 %cmp
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; CHECK: @test15
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; CHECK: ret i1 undef
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}
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define i1 @test16() nounwind readnone {
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entry:
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%cmp = icmp ne i8 undef, -128
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ret i1 %cmp
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; CHECK: @test16
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; CHECK: ret i1 undef
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}
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define i1 @test17(i32 %x) nounwind {
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%shl = shl i32 1, %x
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%and = and i32 %shl, 8
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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; CHECK: @test17
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; CHECK-NEXT: %cmp = icmp ne i32 %x, 3
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}
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define i1 @test18(i32 %x) nounwind {
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%sh = lshr i32 8, %x
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%and = and i32 %sh, 1
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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; CHECK: @test18
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; CHECK-NEXT: %cmp = icmp ne i32 %x, 3
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}
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define i1 @test19(i32 %x) nounwind {
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%shl = shl i32 1, %x
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%and = and i32 %shl, 8
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%cmp = icmp eq i32 %and, 8
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ret i1 %cmp
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; CHECK: @test19
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; CHECK-NEXT: %cmp = icmp eq i32 %x, 3
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}
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define i1 @test20(i32 %x) nounwind {
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%shl = shl i32 1, %x
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%and = and i32 %shl, 8
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%cmp = icmp ne i32 %and, 0
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ret i1 %cmp
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; CHECK: @test20
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; CHECK-NEXT: %cmp = icmp eq i32 %x, 3
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}
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define i1 @test21(i8 %x, i8 %y) {
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; CHECK: @test21
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; CHECK-NOT: or i8
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; CHECK: icmp ugt
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%A = or i8 %x, 1
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%B = icmp ugt i8 %A, 3
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ret i1 %B
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}
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define i1 @test22(i8 %x, i8 %y) {
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; CHECK: @test22
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; CHECK-NOT: or i8
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; CHECK: icmp ult
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%A = or i8 %x, 1
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%B = icmp ult i8 %A, 4
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ret i1 %B
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}
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; PR2740
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; CHECK: @test23
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; CHECK: icmp sgt i32 %x, 1328634634
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define i1 @test23(i32 %x) nounwind {
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%i3 = sdiv i32 %x, -1328634635
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%i4 = icmp eq i32 %i3, -1
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ret i1 %i4
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}
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@X = global [1000 x i32] zeroinitializer
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; PR8882
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; CHECK: @test24
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; CHECK: %cmp = icmp eq i64 %i, 1000
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; CHECK: ret i1 %cmp
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define i1 @test24(i64 %i) {
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%p1 = getelementptr inbounds i32* getelementptr inbounds ([1000 x i32]* @X, i64 0, i64 0), i64 %i
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%cmp = icmp eq i32* %p1, getelementptr inbounds ([1000 x i32]* @X, i64 1, i64 0)
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ret i1 %cmp
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}
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