Nate Begeman 8d5c50329b Add support for the isLoad and isStore flags, needed by the instruction scheduler ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16555 91177308-0d34-0410-b5e6-96231b3b80d8

2004-09-28 21:29:00 +00:00

..

CBackend

Pull assignment out of for loop conditional in order for this to

2004-09-28 02:40:37 +00:00

PowerPC

Correct some BuildMI arguments for the upcoming simple scheduler

2004-09-27 05:08:17 +00:00

Skeleton

Make sure to set the operand list

2004-09-21 17:30:54 +00:00

Sparc

SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!

2004-09-27 18:22:18 +00:00

SparcV8

SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!

2004-09-27 18:22:18 +00:00

SparcV9

Add includes and use std:: for standard library calls to make code

2004-09-28 14:42:44 +00:00

X86

The real x87 floating point registers should not be allocatable. They

2004-09-21 21:22:11 +00:00

Makefile

Targets are independent of each other, so compile them in parallel

2004-09-15 01:34:25 +00:00

MRegisterInfo.cpp

Add getAllocatableSet() function.

2004-08-26 22:21:04 +00:00

Target.td

Add support for the isLoad and isStore flags, needed by the instruction scheduler

2004-09-28 21:29:00 +00:00

TargetData.cpp

Changes For Bug 352

2004-09-01 22:55:40 +00:00

TargetFrameInfo.cpp

Remove dead methods

2004-08-12 18:37:15 +00:00

TargetInstrInfo.cpp

ConstantTypeMustBeLoaded has been incorporated into SparcV9PreSelection, its

2004-07-27 21:43:38 +00:00

TargetMachine.cpp

Changes For Bug 352

2004-09-01 22:55:40 +00:00

TargetMachineRegistry.cpp

Implement TargetRegistrationListener

2004-07-11 06:03:21 +00:00

TargetSchedInfo.cpp

Since we use alloca now make sure we include the proper headers for it.

2004-09-28 02:53:15 +00:00