Matt Arsenault 0b87955888 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec* ...

There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210756 91177308-0d34-0410-b5e6-96231b3b80d8

2014-06-12 08:21:54 +00:00

..

InstPrinter

R600/SI: Prettier display of input modifiers

2014-05-10 19:18:33 +00:00

MCTargetDesc

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TargetInfo

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AMDGPU.h

R600: Add definition for flat address space ID.

2014-05-22 18:27:07 +00:00

AMDGPU.td

R600/SI: Add a PredicateControl class for managing TableGen predicates

2014-05-16 20:56:45 +00:00

AMDGPUAsmPrinter.cpp

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AMDGPUAsmPrinter.h

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AMDGPUCallingConv.td

R600/SI: allow 5 more input SGPRs to a shader

2014-05-05 19:30:54 +00:00

AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

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AMDGPUFrameLowering.h

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AMDGPUInstrInfo.cpp

R600/SI: Refactor the VOP3_32 tablegen class

2014-05-16 20:56:47 +00:00

AMDGPUInstrInfo.h

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AMDGPUInstrInfo.td

R600/SI: Use v_cvt_f32_ubyte* instructions

2014-06-11 17:50:44 +00:00

AMDGPUInstructions.td

R600/SI: Add common 64-bit LDS atomics

2014-06-11 18:08:54 +00:00

AMDGPUIntrinsics.td

R600/SI: Use v_cvt_f32_ubyte* instructions

2014-06-11 17:50:44 +00:00

AMDGPUISelDAGToDAG.cpp

R600/SI: Fix selection failure on scalar_to_vector

2014-06-11 17:40:32 +00:00

AMDGPUISelLowering.cpp

R600/SI: Use v_cvt_f32_ubyte* instructions

2014-06-11 17:50:44 +00:00

AMDGPUISelLowering.h

R600/SI: Use v_cvt_f32_ubyte* instructions

2014-06-11 17:50:44 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.

2014-05-19 14:29:04 +00:00

AMDGPUMCInstLower.h

R600/SI: Refactor the VOP3_32 tablegen class

2014-05-16 20:56:47 +00:00

AMDGPURegisterInfo.cpp

Use range for

2014-05-15 21:44:05 +00:00

AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

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AMDGPUSubtarget.h

R600: Use BCNT_INT for evergreen

2014-06-10 19:18:28 +00:00

AMDGPUTargetMachine.cpp

R600: Add definition for flat address space ID.

2014-05-22 18:27:07 +00:00

AMDGPUTargetMachine.h

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AMDGPUTargetTransformInfo.cpp

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AMDILBase.td

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AMDILCFGStructurizer.cpp

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AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

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AMDILIntrinsics.td

R600/SI: Use bcnt instruction for ctpop

2014-06-10 19:18:21 +00:00

AMDILISelLowering.cpp

R600/SI: Use bcnt instruction for ctpop

2014-06-10 19:18:21 +00:00

AMDILRegisterInfo.td

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CaymanInstructions.td

R600: Expand mul24 for GPUs without it

2014-05-22 18:00:24 +00:00

CMakeLists.txt

R600/SI: Use VALU instructions for copying i1 values

2014-04-30 15:31:33 +00:00

EvergreenInstructions.td

R600: BCNT_INT is a vector only instruction

2014-06-11 20:51:39 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Add processor type for Mullins.

2014-05-02 15:41:49 +00:00

R600ClauseMergePass.cpp

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R600ControlFlowFinalizer.cpp

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R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600InstrFormats.td

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R600InstrInfo.cpp

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R600InstrInfo.h

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R600Instructions.td

R600: Set correct InstrItinClass for instructions using *Helper classes

2014-06-11 20:51:42 +00:00

R600Intrinsics.td

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R600ISelLowering.cpp

R600: Add dag combine for BFE

2014-05-22 18:09:07 +00:00

R600ISelLowering.h

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R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

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R600Packetizer.cpp

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R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

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R700Instructions.td

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SIAnnotateControlFlow.cpp

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SIDefines.h

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SIFixSGPRCopies.cpp

R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies

2014-05-15 14:41:55 +00:00

SIInsertWaits.cpp

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SIInstrFormats.td

R600/SI: Add a PredicateControl class for managing TableGen predicates

2014-05-16 20:56:45 +00:00

SIInstrInfo.cpp

R600/SI: Emit an error when attempting to spill VGPRs v4

2014-06-10 21:20:41 +00:00

SIInstrInfo.h

R600/SI: Implement i64 ctpop

2014-06-10 19:18:24 +00:00

SIInstrInfo.td

R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*

2014-06-12 08:21:54 +00:00

SIInstructions.td

R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*

2014-06-12 08:21:54 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

R600/SI: Use v_cvt_f32_ubyte* instructions

2014-06-11 17:50:44 +00:00

SIISelLowering.h

R600/SI: Use v_cvt_f32_ubyte* instructions

2014-06-11 17:50:44 +00:00

SILowerControlFlow.cpp

R600/SI: Use VALU instructions for copying i1 values

2014-04-30 15:31:33 +00:00

SILowerI1Copies.cpp

R600/SI: Use VALU instructions for i1 ops

2014-05-15 14:41:50 +00:00

SIMachineFunctionInfo.cpp

R600/SI: Only create one instruction when spilling/restoring register v3

2014-05-02 15:41:42 +00:00

SIMachineFunctionInfo.h

R600/SI: Only create one instruction when spilling/restoring register v3

2014-05-02 15:41:42 +00:00

SIRegisterInfo.cpp

Use range for

2014-05-12 19:23:21 +00:00

SIRegisterInfo.h

R600/SI: Only create one instruction when spilling/restoring register v3

2014-05-02 15:41:42 +00:00

SIRegisterInfo.td

R600/SI: Use VALU instructions for copying i1 values

2014-04-30 15:31:33 +00:00

SISchedule.td

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SITypeRewriter.cpp

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