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https://github.com/c64scene-ar/llvm-6502.git
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b99395a7f7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227293 91177308-0d34-0410-b5e6-96231b3b80d8
966 lines
33 KiB
C++
966 lines
33 KiB
C++
//=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that performs load / store related peephole
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// optimizations. This pass should be run after register allocation.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64InstrInfo.h"
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#include "AArch64Subtarget.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-ldst-opt"
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/// AArch64AllocLoadStoreOpt - Post-register allocation pass to combine
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/// load / store instructions to form ldp / stp instructions.
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STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
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STATISTIC(NumPostFolded, "Number of post-index updates folded");
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STATISTIC(NumPreFolded, "Number of pre-index updates folded");
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STATISTIC(NumUnscaledPairCreated,
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"Number of load/store from unscaled generated");
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static cl::opt<unsigned> ScanLimit("aarch64-load-store-scan-limit",
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cl::init(20), cl::Hidden);
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// Place holder while testing unscaled load/store combining
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static cl::opt<bool> EnableAArch64UnscaledMemOp(
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"aarch64-unscaled-mem-op", cl::Hidden,
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cl::desc("Allow AArch64 unscaled load/store combining"), cl::init(true));
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namespace {
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struct AArch64LoadStoreOpt : public MachineFunctionPass {
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static char ID;
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AArch64LoadStoreOpt() : MachineFunctionPass(ID) {}
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const AArch64InstrInfo *TII;
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const TargetRegisterInfo *TRI;
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// Scan the instructions looking for a load/store that can be combined
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// with the current instruction into a load/store pair.
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// Return the matching instruction if one is found, else MBB->end().
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// If a matching instruction is found, MergeForward is set to true if the
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// merge is to remove the first instruction and replace the second with
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// a pair-wise insn, and false if the reverse is true.
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MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
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bool &MergeForward,
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unsigned Limit);
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// Merge the two instructions indicated into a single pair-wise instruction.
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// If MergeForward is true, erase the first instruction and fold its
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// operation into the second. If false, the reverse. Return the instruction
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// following the first instruction (which may change during processing).
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MachineBasicBlock::iterator
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mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired, bool MergeForward);
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// Scan the instruction list to find a base register update that can
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// be combined with the current instruction (a load or store) using
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// pre or post indexed addressing with writeback. Scan forwards.
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MachineBasicBlock::iterator
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findMatchingUpdateInsnForward(MachineBasicBlock::iterator I, unsigned Limit,
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int Value);
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// Scan the instruction list to find a base register update that can
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// be combined with the current instruction (a load or store) using
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// pre or post indexed addressing with writeback. Scan backwards.
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MachineBasicBlock::iterator
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findMatchingUpdateInsnBackward(MachineBasicBlock::iterator I, unsigned Limit);
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// Merge a pre-index base register update into a ld/st instruction.
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MachineBasicBlock::iterator
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mergePreIdxUpdateInsn(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Update);
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// Merge a post-index base register update into a ld/st instruction.
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MachineBasicBlock::iterator
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mergePostIdxUpdateInsn(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Update);
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bool optimizeBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &Fn) override;
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const char *getPassName() const override {
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return "AArch64 load / store optimization pass";
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}
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private:
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int getMemSize(MachineInstr *MemMI);
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};
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char AArch64LoadStoreOpt::ID = 0;
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} // namespace
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static bool isUnscaledLdst(unsigned Opc) {
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switch (Opc) {
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default:
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return false;
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case AArch64::STURSi:
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return true;
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case AArch64::STURDi:
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return true;
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case AArch64::STURQi:
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return true;
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case AArch64::STURWi:
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return true;
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case AArch64::STURXi:
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return true;
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case AArch64::LDURSi:
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return true;
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case AArch64::LDURDi:
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return true;
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case AArch64::LDURQi:
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return true;
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case AArch64::LDURWi:
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return true;
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case AArch64::LDURXi:
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return true;
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case AArch64::LDURSWi:
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return true;
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}
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}
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// Size in bytes of the data moved by an unscaled load or store
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int AArch64LoadStoreOpt::getMemSize(MachineInstr *MemMI) {
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switch (MemMI->getOpcode()) {
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default:
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llvm_unreachable("Opcode has unknown size!");
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case AArch64::STRSui:
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case AArch64::STURSi:
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return 4;
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case AArch64::STRDui:
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case AArch64::STURDi:
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return 8;
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case AArch64::STRQui:
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case AArch64::STURQi:
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return 16;
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case AArch64::STRWui:
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case AArch64::STURWi:
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return 4;
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case AArch64::STRXui:
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case AArch64::STURXi:
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return 8;
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case AArch64::LDRSui:
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case AArch64::LDURSi:
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return 4;
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case AArch64::LDRDui:
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case AArch64::LDURDi:
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return 8;
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case AArch64::LDRQui:
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case AArch64::LDURQi:
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return 16;
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case AArch64::LDRWui:
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case AArch64::LDURWi:
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return 4;
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case AArch64::LDRXui:
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case AArch64::LDURXi:
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return 8;
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case AArch64::LDRSWui:
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case AArch64::LDURSWi:
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return 4;
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}
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}
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static unsigned getMatchingPairOpcode(unsigned Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Opcode has no pairwise equivalent!");
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case AArch64::STRSui:
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case AArch64::STURSi:
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return AArch64::STPSi;
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case AArch64::STRDui:
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case AArch64::STURDi:
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return AArch64::STPDi;
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case AArch64::STRQui:
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case AArch64::STURQi:
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return AArch64::STPQi;
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case AArch64::STRWui:
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case AArch64::STURWi:
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return AArch64::STPWi;
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case AArch64::STRXui:
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case AArch64::STURXi:
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return AArch64::STPXi;
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case AArch64::LDRSui:
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case AArch64::LDURSi:
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return AArch64::LDPSi;
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case AArch64::LDRDui:
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case AArch64::LDURDi:
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return AArch64::LDPDi;
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case AArch64::LDRQui:
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case AArch64::LDURQi:
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return AArch64::LDPQi;
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case AArch64::LDRWui:
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case AArch64::LDURWi:
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return AArch64::LDPWi;
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case AArch64::LDRXui:
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case AArch64::LDURXi:
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return AArch64::LDPXi;
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case AArch64::LDRSWui:
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case AArch64::LDURSWi:
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return AArch64::LDPSWi;
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}
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}
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static unsigned getPreIndexedOpcode(unsigned Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Opcode has no pre-indexed equivalent!");
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case AArch64::STRSui:
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return AArch64::STRSpre;
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case AArch64::STRDui:
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return AArch64::STRDpre;
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case AArch64::STRQui:
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return AArch64::STRQpre;
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case AArch64::STRWui:
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return AArch64::STRWpre;
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case AArch64::STRXui:
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return AArch64::STRXpre;
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case AArch64::LDRSui:
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return AArch64::LDRSpre;
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case AArch64::LDRDui:
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return AArch64::LDRDpre;
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case AArch64::LDRQui:
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return AArch64::LDRQpre;
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case AArch64::LDRWui:
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return AArch64::LDRWpre;
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case AArch64::LDRXui:
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return AArch64::LDRXpre;
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case AArch64::LDRSWui:
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return AArch64::LDRSWpre;
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}
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}
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static unsigned getPostIndexedOpcode(unsigned Opc) {
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switch (Opc) {
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default:
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llvm_unreachable("Opcode has no post-indexed wise equivalent!");
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case AArch64::STRSui:
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return AArch64::STRSpost;
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case AArch64::STRDui:
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return AArch64::STRDpost;
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case AArch64::STRQui:
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return AArch64::STRQpost;
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case AArch64::STRWui:
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return AArch64::STRWpost;
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case AArch64::STRXui:
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return AArch64::STRXpost;
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case AArch64::LDRSui:
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return AArch64::LDRSpost;
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case AArch64::LDRDui:
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return AArch64::LDRDpost;
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case AArch64::LDRQui:
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return AArch64::LDRQpost;
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case AArch64::LDRWui:
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return AArch64::LDRWpost;
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case AArch64::LDRXui:
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return AArch64::LDRXpost;
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case AArch64::LDRSWui:
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return AArch64::LDRSWpost;
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}
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}
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MachineBasicBlock::iterator
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AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator Paired,
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bool MergeForward) {
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MachineBasicBlock::iterator NextI = I;
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++NextI;
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// If NextI is the second of the two instructions to be merged, we need
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// to skip one further. Either way we merge will invalidate the iterator,
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// and we don't need to scan the new instruction, as it's a pairwise
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// instruction, which we're not considering for further action anyway.
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if (NextI == Paired)
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++NextI;
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bool IsUnscaled = isUnscaledLdst(I->getOpcode());
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int OffsetStride =
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IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(I) : 1;
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unsigned NewOpc = getMatchingPairOpcode(I->getOpcode());
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// Insert our new paired instruction after whichever of the paired
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// instructions MergeForward indicates.
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MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
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// Also based on MergeForward is from where we copy the base register operand
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// so we get the flags compatible with the input code.
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MachineOperand &BaseRegOp =
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MergeForward ? Paired->getOperand(1) : I->getOperand(1);
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// Which register is Rt and which is Rt2 depends on the offset order.
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MachineInstr *RtMI, *Rt2MI;
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if (I->getOperand(2).getImm() ==
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Paired->getOperand(2).getImm() + OffsetStride) {
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RtMI = Paired;
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Rt2MI = I;
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} else {
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RtMI = I;
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Rt2MI = Paired;
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}
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// Handle Unscaled
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int OffsetImm = RtMI->getOperand(2).getImm();
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if (IsUnscaled && EnableAArch64UnscaledMemOp)
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OffsetImm /= OffsetStride;
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// Construct the new instruction.
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MachineInstrBuilder MIB = BuildMI(*I->getParent(), InsertionPoint,
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I->getDebugLoc(), TII->get(NewOpc))
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.addOperand(RtMI->getOperand(0))
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.addOperand(Rt2MI->getOperand(0))
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.addOperand(BaseRegOp)
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.addImm(OffsetImm);
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(void)MIB;
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// FIXME: Do we need/want to copy the mem operands from the source
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// instructions? Probably. What uses them after this?
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DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n ");
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DEBUG(I->print(dbgs()));
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DEBUG(dbgs() << " ");
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DEBUG(Paired->print(dbgs()));
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DEBUG(dbgs() << " with instruction:\n ");
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DEBUG(((MachineInstr *)MIB)->print(dbgs()));
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DEBUG(dbgs() << "\n");
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// Erase the old instructions.
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I->eraseFromParent();
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Paired->eraseFromParent();
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return NextI;
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}
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/// trackRegDefsUses - Remember what registers the specified instruction uses
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/// and modifies.
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static void trackRegDefsUses(MachineInstr *MI, BitVector &ModifiedRegs,
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BitVector &UsedRegs,
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const TargetRegisterInfo *TRI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegMask())
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ModifiedRegs.setBitsNotInMask(MO.getRegMask());
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (MO.isDef()) {
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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ModifiedRegs.set(*AI);
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} else {
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assert(MO.isUse() && "Reg operand not a def and not a use?!?");
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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UsedRegs.set(*AI);
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}
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}
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}
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static bool inBoundsForPair(bool IsUnscaled, int Offset, int OffsetStride) {
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if (!IsUnscaled && (Offset > 63 || Offset < -64))
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return false;
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if (IsUnscaled) {
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// Convert the byte-offset used by unscaled into an "element" offset used
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// by the scaled pair load/store instructions.
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int ElemOffset = Offset / OffsetStride;
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if (ElemOffset > 63 || ElemOffset < -64)
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return false;
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}
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return true;
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}
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// Do alignment, specialized to power of 2 and for signed ints,
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// avoiding having to do a C-style cast from uint_64t to int when
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// using RoundUpToAlignment from include/llvm/Support/MathExtras.h.
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// FIXME: Move this function to include/MathExtras.h?
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static int alignTo(int Num, int PowOf2) {
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return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
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}
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/// findMatchingInsn - Scan the instructions looking for a load/store that can
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/// be combined with the current instruction into a load/store pair.
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MachineBasicBlock::iterator
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AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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bool &MergeForward, unsigned Limit) {
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MachineBasicBlock::iterator E = I->getParent()->end();
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MachineBasicBlock::iterator MBBI = I;
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MachineInstr *FirstMI = I;
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++MBBI;
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int Opc = FirstMI->getOpcode();
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bool MayLoad = FirstMI->mayLoad();
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bool IsUnscaled = isUnscaledLdst(Opc);
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unsigned Reg = FirstMI->getOperand(0).getReg();
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unsigned BaseReg = FirstMI->getOperand(1).getReg();
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int Offset = FirstMI->getOperand(2).getImm();
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// Early exit if the first instruction modifies the base register.
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// e.g., ldr x0, [x0]
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// Early exit if the offset if not possible to match. (6 bits of positive
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// range, plus allow an extra one in case we find a later insn that matches
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// with Offset-1
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if (FirstMI->modifiesRegister(BaseReg, TRI))
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return E;
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int OffsetStride =
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IsUnscaled && EnableAArch64UnscaledMemOp ? getMemSize(FirstMI) : 1;
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if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride))
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return E;
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// Track which registers have been modified and used between the first insn
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// (inclusive) and the second insn.
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BitVector ModifiedRegs, UsedRegs;
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ModifiedRegs.resize(TRI->getNumRegs());
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UsedRegs.resize(TRI->getNumRegs());
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for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
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MachineInstr *MI = MBBI;
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// Skip DBG_VALUE instructions. Otherwise debug info can affect the
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// optimization by changing how far we scan.
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if (MI->isDebugValue())
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continue;
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// Now that we know this is a real instruction, count it.
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++Count;
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if (Opc == MI->getOpcode() && MI->getOperand(2).isImm()) {
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// If we've found another instruction with the same opcode, check to see
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// if the base and offset are compatible with our starting instruction.
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// These instructions all have scaled immediate operands, so we just
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// check for +1/-1. Make sure to check the new instruction offset is
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// actually an immediate and not a symbolic reference destined for
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// a relocation.
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//
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// Pairwise instructions have a 7-bit signed offset field. Single insns
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// have a 12-bit unsigned offset field. To be a valid combine, the
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// final offset must be in range.
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unsigned MIBaseReg = MI->getOperand(1).getReg();
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int MIOffset = MI->getOperand(2).getImm();
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if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
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(Offset + OffsetStride == MIOffset))) {
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int MinOffset = Offset < MIOffset ? Offset : MIOffset;
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// If this is a volatile load/store that otherwise matched, stop looking
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// as something is going on that we don't have enough information to
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// safely transform. Similarly, stop if we see a hint to avoid pairs.
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if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
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return E;
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// If the resultant immediate offset of merging these instructions
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// is out of range for a pairwise instruction, bail and keep looking.
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bool MIIsUnscaled = isUnscaledLdst(MI->getOpcode());
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if (!inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
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trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
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continue;
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}
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// If the alignment requirements of the paired (scaled) instruction
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// can't express the offset of the unscaled input, bail and keep
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|
// looking.
|
|
if (IsUnscaled && EnableAArch64UnscaledMemOp &&
|
|
(alignTo(MinOffset, OffsetStride) != MinOffset)) {
|
|
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
|
|
continue;
|
|
}
|
|
// If the destination register of the loads is the same register, bail
|
|
// and keep looking. A load-pair instruction with both destination
|
|
// registers the same is UNPREDICTABLE and will result in an exception.
|
|
if (MayLoad && Reg == MI->getOperand(0).getReg()) {
|
|
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
|
|
continue;
|
|
}
|
|
|
|
// If the Rt of the second instruction was not modified or used between
|
|
// the two instructions, we can combine the second into the first.
|
|
if (!ModifiedRegs[MI->getOperand(0).getReg()] &&
|
|
!UsedRegs[MI->getOperand(0).getReg()]) {
|
|
MergeForward = false;
|
|
return MBBI;
|
|
}
|
|
|
|
// Likewise, if the Rt of the first instruction is not modified or used
|
|
// between the two instructions, we can combine the first into the
|
|
// second.
|
|
if (!ModifiedRegs[FirstMI->getOperand(0).getReg()] &&
|
|
!UsedRegs[FirstMI->getOperand(0).getReg()]) {
|
|
MergeForward = true;
|
|
return MBBI;
|
|
}
|
|
// Unable to combine these instructions due to interference in between.
|
|
// Keep looking.
|
|
}
|
|
}
|
|
|
|
// If the instruction wasn't a matching load or store, but does (or can)
|
|
// modify memory, stop searching, as we don't have alias analysis or
|
|
// anything like that to tell us whether the access is tromping on the
|
|
// locations we care about. The big one we want to catch is calls.
|
|
//
|
|
// FIXME: Theoretically, we can do better than that for SP and FP based
|
|
// references since we can effectively know where those are touching. It's
|
|
// unclear if it's worth the extra code, though. Most paired instructions
|
|
// will be sequential, perhaps with a few intervening non-memory related
|
|
// instructions.
|
|
if (MI->mayStore() || MI->isCall())
|
|
return E;
|
|
// Likewise, if we're matching a store instruction, we don't want to
|
|
// move across a load, as it may be reading the same location.
|
|
if (FirstMI->mayStore() && MI->mayLoad())
|
|
return E;
|
|
|
|
// Update modified / uses register lists.
|
|
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
|
|
|
|
// Otherwise, if the base register is modified, we have no match, so
|
|
// return early.
|
|
if (ModifiedRegs[BaseReg])
|
|
return E;
|
|
}
|
|
return E;
|
|
}
|
|
|
|
MachineBasicBlock::iterator
|
|
AArch64LoadStoreOpt::mergePreIdxUpdateInsn(MachineBasicBlock::iterator I,
|
|
MachineBasicBlock::iterator Update) {
|
|
assert((Update->getOpcode() == AArch64::ADDXri ||
|
|
Update->getOpcode() == AArch64::SUBXri) &&
|
|
"Unexpected base register update instruction to merge!");
|
|
MachineBasicBlock::iterator NextI = I;
|
|
// Return the instruction following the merged instruction, which is
|
|
// the instruction following our unmerged load. Unless that's the add/sub
|
|
// instruction we're merging, in which case it's the one after that.
|
|
if (++NextI == Update)
|
|
++NextI;
|
|
|
|
int Value = Update->getOperand(2).getImm();
|
|
assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
|
|
"Can't merge 1 << 12 offset into pre-indexed load / store");
|
|
if (Update->getOpcode() == AArch64::SUBXri)
|
|
Value = -Value;
|
|
|
|
unsigned NewOpc = getPreIndexedOpcode(I->getOpcode());
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
|
|
.addOperand(Update->getOperand(0))
|
|
.addOperand(I->getOperand(0))
|
|
.addOperand(I->getOperand(1))
|
|
.addImm(Value);
|
|
(void)MIB;
|
|
|
|
DEBUG(dbgs() << "Creating pre-indexed load/store.");
|
|
DEBUG(dbgs() << " Replacing instructions:\n ");
|
|
DEBUG(I->print(dbgs()));
|
|
DEBUG(dbgs() << " ");
|
|
DEBUG(Update->print(dbgs()));
|
|
DEBUG(dbgs() << " with instruction:\n ");
|
|
DEBUG(((MachineInstr *)MIB)->print(dbgs()));
|
|
DEBUG(dbgs() << "\n");
|
|
|
|
// Erase the old instructions for the block.
|
|
I->eraseFromParent();
|
|
Update->eraseFromParent();
|
|
|
|
return NextI;
|
|
}
|
|
|
|
MachineBasicBlock::iterator AArch64LoadStoreOpt::mergePostIdxUpdateInsn(
|
|
MachineBasicBlock::iterator I, MachineBasicBlock::iterator Update) {
|
|
assert((Update->getOpcode() == AArch64::ADDXri ||
|
|
Update->getOpcode() == AArch64::SUBXri) &&
|
|
"Unexpected base register update instruction to merge!");
|
|
MachineBasicBlock::iterator NextI = I;
|
|
// Return the instruction following the merged instruction, which is
|
|
// the instruction following our unmerged load. Unless that's the add/sub
|
|
// instruction we're merging, in which case it's the one after that.
|
|
if (++NextI == Update)
|
|
++NextI;
|
|
|
|
int Value = Update->getOperand(2).getImm();
|
|
assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
|
|
"Can't merge 1 << 12 offset into post-indexed load / store");
|
|
if (Update->getOpcode() == AArch64::SUBXri)
|
|
Value = -Value;
|
|
|
|
unsigned NewOpc = getPostIndexedOpcode(I->getOpcode());
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
|
|
.addOperand(Update->getOperand(0))
|
|
.addOperand(I->getOperand(0))
|
|
.addOperand(I->getOperand(1))
|
|
.addImm(Value);
|
|
(void)MIB;
|
|
|
|
DEBUG(dbgs() << "Creating post-indexed load/store.");
|
|
DEBUG(dbgs() << " Replacing instructions:\n ");
|
|
DEBUG(I->print(dbgs()));
|
|
DEBUG(dbgs() << " ");
|
|
DEBUG(Update->print(dbgs()));
|
|
DEBUG(dbgs() << " with instruction:\n ");
|
|
DEBUG(((MachineInstr *)MIB)->print(dbgs()));
|
|
DEBUG(dbgs() << "\n");
|
|
|
|
// Erase the old instructions for the block.
|
|
I->eraseFromParent();
|
|
Update->eraseFromParent();
|
|
|
|
return NextI;
|
|
}
|
|
|
|
static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg,
|
|
int Offset) {
|
|
switch (MI->getOpcode()) {
|
|
default:
|
|
break;
|
|
case AArch64::SUBXri:
|
|
// Negate the offset for a SUB instruction.
|
|
Offset *= -1;
|
|
// FALLTHROUGH
|
|
case AArch64::ADDXri:
|
|
// Make sure it's a vanilla immediate operand, not a relocation or
|
|
// anything else we can't handle.
|
|
if (!MI->getOperand(2).isImm())
|
|
break;
|
|
// Watch out for 1 << 12 shifted value.
|
|
if (AArch64_AM::getShiftValue(MI->getOperand(3).getImm()))
|
|
break;
|
|
// If the instruction has the base register as source and dest and the
|
|
// immediate will fit in a signed 9-bit integer, then we have a match.
|
|
if (MI->getOperand(0).getReg() == BaseReg &&
|
|
MI->getOperand(1).getReg() == BaseReg &&
|
|
MI->getOperand(2).getImm() <= 255 &&
|
|
MI->getOperand(2).getImm() >= -256) {
|
|
// If we have a non-zero Offset, we check that it matches the amount
|
|
// we're adding to the register.
|
|
if (!Offset || Offset == MI->getOperand(2).getImm())
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
|
|
MachineBasicBlock::iterator I, unsigned Limit, int Value) {
|
|
MachineBasicBlock::iterator E = I->getParent()->end();
|
|
MachineInstr *MemMI = I;
|
|
MachineBasicBlock::iterator MBBI = I;
|
|
const MachineFunction &MF = *MemMI->getParent()->getParent();
|
|
|
|
unsigned DestReg = MemMI->getOperand(0).getReg();
|
|
unsigned BaseReg = MemMI->getOperand(1).getReg();
|
|
int Offset = MemMI->getOperand(2).getImm() *
|
|
TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
|
|
|
|
// If the base register overlaps the destination register, we can't
|
|
// merge the update.
|
|
if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
|
|
return E;
|
|
|
|
// Scan forward looking for post-index opportunities.
|
|
// Updating instructions can't be formed if the memory insn already
|
|
// has an offset other than the value we're looking for.
|
|
if (Offset != Value)
|
|
return E;
|
|
|
|
// Track which registers have been modified and used between the first insn
|
|
// (inclusive) and the second insn.
|
|
BitVector ModifiedRegs, UsedRegs;
|
|
ModifiedRegs.resize(TRI->getNumRegs());
|
|
UsedRegs.resize(TRI->getNumRegs());
|
|
++MBBI;
|
|
for (unsigned Count = 0; MBBI != E; ++MBBI) {
|
|
MachineInstr *MI = MBBI;
|
|
// Skip DBG_VALUE instructions. Otherwise debug info can affect the
|
|
// optimization by changing how far we scan.
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
// Now that we know this is a real instruction, count it.
|
|
++Count;
|
|
|
|
// If we found a match, return it.
|
|
if (isMatchingUpdateInsn(MI, BaseReg, Value))
|
|
return MBBI;
|
|
|
|
// Update the status of what the instruction clobbered and used.
|
|
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
|
|
|
|
// Otherwise, if the base register is used or modified, we have no match, so
|
|
// return early.
|
|
if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
|
|
return E;
|
|
}
|
|
return E;
|
|
}
|
|
|
|
MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
|
|
MachineBasicBlock::iterator I, unsigned Limit) {
|
|
MachineBasicBlock::iterator B = I->getParent()->begin();
|
|
MachineBasicBlock::iterator E = I->getParent()->end();
|
|
MachineInstr *MemMI = I;
|
|
MachineBasicBlock::iterator MBBI = I;
|
|
const MachineFunction &MF = *MemMI->getParent()->getParent();
|
|
|
|
unsigned DestReg = MemMI->getOperand(0).getReg();
|
|
unsigned BaseReg = MemMI->getOperand(1).getReg();
|
|
int Offset = MemMI->getOperand(2).getImm();
|
|
unsigned RegSize = TII->getRegClass(MemMI->getDesc(), 0, TRI, MF)->getSize();
|
|
|
|
// If the load/store is the first instruction in the block, there's obviously
|
|
// not any matching update. Ditto if the memory offset isn't zero.
|
|
if (MBBI == B || Offset != 0)
|
|
return E;
|
|
// If the base register overlaps the destination register, we can't
|
|
// merge the update.
|
|
if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
|
|
return E;
|
|
|
|
// Track which registers have been modified and used between the first insn
|
|
// (inclusive) and the second insn.
|
|
BitVector ModifiedRegs, UsedRegs;
|
|
ModifiedRegs.resize(TRI->getNumRegs());
|
|
UsedRegs.resize(TRI->getNumRegs());
|
|
--MBBI;
|
|
for (unsigned Count = 0; MBBI != B; --MBBI) {
|
|
MachineInstr *MI = MBBI;
|
|
// Skip DBG_VALUE instructions. Otherwise debug info can affect the
|
|
// optimization by changing how far we scan.
|
|
if (MI->isDebugValue())
|
|
continue;
|
|
|
|
// Now that we know this is a real instruction, count it.
|
|
++Count;
|
|
|
|
// If we found a match, return it.
|
|
if (isMatchingUpdateInsn(MI, BaseReg, RegSize))
|
|
return MBBI;
|
|
|
|
// Update the status of what the instruction clobbered and used.
|
|
trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
|
|
|
|
// Otherwise, if the base register is used or modified, we have no match, so
|
|
// return early.
|
|
if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
|
|
return E;
|
|
}
|
|
return E;
|
|
}
|
|
|
|
bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB) {
|
|
bool Modified = false;
|
|
// Two tranformations to do here:
|
|
// 1) Find loads and stores that can be merged into a single load or store
|
|
// pair instruction.
|
|
// e.g.,
|
|
// ldr x0, [x2]
|
|
// ldr x1, [x2, #8]
|
|
// ; becomes
|
|
// ldp x0, x1, [x2]
|
|
// 2) Find base register updates that can be merged into the load or store
|
|
// as a base-reg writeback.
|
|
// e.g.,
|
|
// ldr x0, [x2]
|
|
// add x2, x2, #4
|
|
// ; becomes
|
|
// ldr x0, [x2], #4
|
|
|
|
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
MBBI != E;) {
|
|
MachineInstr *MI = MBBI;
|
|
switch (MI->getOpcode()) {
|
|
default:
|
|
// Just move on to the next instruction.
|
|
++MBBI;
|
|
break;
|
|
case AArch64::STRSui:
|
|
case AArch64::STRDui:
|
|
case AArch64::STRQui:
|
|
case AArch64::STRXui:
|
|
case AArch64::STRWui:
|
|
case AArch64::LDRSui:
|
|
case AArch64::LDRDui:
|
|
case AArch64::LDRQui:
|
|
case AArch64::LDRXui:
|
|
case AArch64::LDRWui:
|
|
case AArch64::LDRSWui:
|
|
// do the unscaled versions as well
|
|
case AArch64::STURSi:
|
|
case AArch64::STURDi:
|
|
case AArch64::STURQi:
|
|
case AArch64::STURWi:
|
|
case AArch64::STURXi:
|
|
case AArch64::LDURSi:
|
|
case AArch64::LDURDi:
|
|
case AArch64::LDURQi:
|
|
case AArch64::LDURWi:
|
|
case AArch64::LDURXi:
|
|
case AArch64::LDURSWi: {
|
|
// If this is a volatile load/store, don't mess with it.
|
|
if (MI->hasOrderedMemoryRef()) {
|
|
++MBBI;
|
|
break;
|
|
}
|
|
// Make sure this is a reg+imm (as opposed to an address reloc).
|
|
if (!MI->getOperand(2).isImm()) {
|
|
++MBBI;
|
|
break;
|
|
}
|
|
// Check if this load/store has a hint to avoid pair formation.
|
|
// MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
|
|
if (TII->isLdStPairSuppressed(MI)) {
|
|
++MBBI;
|
|
break;
|
|
}
|
|
// Look ahead up to ScanLimit instructions for a pairable instruction.
|
|
bool MergeForward = false;
|
|
MachineBasicBlock::iterator Paired =
|
|
findMatchingInsn(MBBI, MergeForward, ScanLimit);
|
|
if (Paired != E) {
|
|
// Merge the loads into a pair. Keeping the iterator straight is a
|
|
// pain, so we let the merge routine tell us what the next instruction
|
|
// is after it's done mucking about.
|
|
MBBI = mergePairedInsns(MBBI, Paired, MergeForward);
|
|
|
|
Modified = true;
|
|
++NumPairCreated;
|
|
if (isUnscaledLdst(MI->getOpcode()))
|
|
++NumUnscaledPairCreated;
|
|
break;
|
|
}
|
|
++MBBI;
|
|
break;
|
|
}
|
|
// FIXME: Do the other instructions.
|
|
}
|
|
}
|
|
|
|
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
MBBI != E;) {
|
|
MachineInstr *MI = MBBI;
|
|
// Do update merging. It's simpler to keep this separate from the above
|
|
// switch, though not strictly necessary.
|
|
int Opc = MI->getOpcode();
|
|
switch (Opc) {
|
|
default:
|
|
// Just move on to the next instruction.
|
|
++MBBI;
|
|
break;
|
|
case AArch64::STRSui:
|
|
case AArch64::STRDui:
|
|
case AArch64::STRQui:
|
|
case AArch64::STRXui:
|
|
case AArch64::STRWui:
|
|
case AArch64::LDRSui:
|
|
case AArch64::LDRDui:
|
|
case AArch64::LDRQui:
|
|
case AArch64::LDRXui:
|
|
case AArch64::LDRWui:
|
|
// do the unscaled versions as well
|
|
case AArch64::STURSi:
|
|
case AArch64::STURDi:
|
|
case AArch64::STURQi:
|
|
case AArch64::STURWi:
|
|
case AArch64::STURXi:
|
|
case AArch64::LDURSi:
|
|
case AArch64::LDURDi:
|
|
case AArch64::LDURQi:
|
|
case AArch64::LDURWi:
|
|
case AArch64::LDURXi: {
|
|
// Make sure this is a reg+imm (as opposed to an address reloc).
|
|
if (!MI->getOperand(2).isImm()) {
|
|
++MBBI;
|
|
break;
|
|
}
|
|
// Look ahead up to ScanLimit instructions for a mergable instruction.
|
|
MachineBasicBlock::iterator Update =
|
|
findMatchingUpdateInsnForward(MBBI, ScanLimit, 0);
|
|
if (Update != E) {
|
|
// Merge the update into the ld/st.
|
|
MBBI = mergePostIdxUpdateInsn(MBBI, Update);
|
|
Modified = true;
|
|
++NumPostFolded;
|
|
break;
|
|
}
|
|
// Don't know how to handle pre/post-index versions, so move to the next
|
|
// instruction.
|
|
if (isUnscaledLdst(Opc)) {
|
|
++MBBI;
|
|
break;
|
|
}
|
|
|
|
// Look back to try to find a pre-index instruction. For example,
|
|
// add x0, x0, #8
|
|
// ldr x1, [x0]
|
|
// merged into:
|
|
// ldr x1, [x0, #8]!
|
|
Update = findMatchingUpdateInsnBackward(MBBI, ScanLimit);
|
|
if (Update != E) {
|
|
// Merge the update into the ld/st.
|
|
MBBI = mergePreIdxUpdateInsn(MBBI, Update);
|
|
Modified = true;
|
|
++NumPreFolded;
|
|
break;
|
|
}
|
|
|
|
// Look forward to try to find a post-index instruction. For example,
|
|
// ldr x1, [x0, #64]
|
|
// add x0, x0, #64
|
|
// merged into:
|
|
// ldr x1, [x0, #64]!
|
|
|
|
// The immediate in the load/store is scaled by the size of the register
|
|
// being loaded. The immediate in the add we're looking for,
|
|
// however, is not, so adjust here.
|
|
int Value = MI->getOperand(2).getImm() *
|
|
TII->getRegClass(MI->getDesc(), 0, TRI, *(MBB.getParent()))
|
|
->getSize();
|
|
Update = findMatchingUpdateInsnForward(MBBI, ScanLimit, Value);
|
|
if (Update != E) {
|
|
// Merge the update into the ld/st.
|
|
MBBI = mergePreIdxUpdateInsn(MBBI, Update);
|
|
Modified = true;
|
|
++NumPreFolded;
|
|
break;
|
|
}
|
|
|
|
// Nothing found. Just move to the next instruction.
|
|
++MBBI;
|
|
break;
|
|
}
|
|
// FIXME: Do the other instructions.
|
|
}
|
|
}
|
|
|
|
return Modified;
|
|
}
|
|
|
|
bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
|
|
TII = static_cast<const AArch64InstrInfo *>(Fn.getSubtarget().getInstrInfo());
|
|
TRI = Fn.getSubtarget().getRegisterInfo();
|
|
|
|
bool Modified = false;
|
|
for (auto &MBB : Fn)
|
|
Modified |= optimizeBlock(MBB);
|
|
|
|
return Modified;
|
|
}
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// FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep
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// loads and stores near one another?
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/// createARMLoadStoreOptimizationPass - returns an instance of the load / store
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/// optimization pass.
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FunctionPass *llvm::createAArch64LoadStoreOptimizationPass() {
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return new AArch64LoadStoreOpt();
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}
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