mirror of
https://github.com/c64scene-ar/llvm-6502.git
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26bc071088
preferences interface on TTI now that all of TTI is per-function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227741 91177308-0d34-0410-b5e6-96231b3b80d8
512 lines
18 KiB
C++
512 lines
18 KiB
C++
//===-- AArch64TargetTransformInfo.cpp - AArch64 specific TTI -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetTransformInfo.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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#include <algorithm>
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using namespace llvm;
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#define DEBUG_TYPE "aarch64tti"
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/// \brief Calculate the cost of materializing a 64-bit value. This helper
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/// method might only calculate a fraction of a larger immediate. Therefore it
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/// is valid to return a cost of ZERO.
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unsigned AArch64TTIImpl::getIntImmCost(int64_t Val) {
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// Check if the immediate can be encoded within an instruction.
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if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, 64))
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return 0;
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if (Val < 0)
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Val = ~Val;
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// Calculate how many moves we will need to materialize this constant.
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unsigned LZ = countLeadingZeros((uint64_t)Val);
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return (64 - LZ + 15) / 16;
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}
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/// \brief Calculate the cost of materializing the given constant.
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unsigned AArch64TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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if (BitSize == 0)
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return ~0U;
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// Sign-extend all constants to a multiple of 64-bit.
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APInt ImmVal = Imm;
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if (BitSize & 0x3f)
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ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
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// Split the constant into 64-bit chunks and calculate the cost for each
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// chunk.
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unsigned Cost = 0;
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for (unsigned ShiftVal = 0; ShiftVal < BitSize; ShiftVal += 64) {
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APInt Tmp = ImmVal.ashr(ShiftVal).sextOrTrunc(64);
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int64_t Val = Tmp.getSExtValue();
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Cost += getIntImmCost(Val);
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}
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// We need at least one instruction to materialze the constant.
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return std::max(1U, Cost);
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}
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unsigned AArch64TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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unsigned ImmIdx = ~0U;
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switch (Opcode) {
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default:
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return TTI::TCC_Free;
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case Instruction::GetElementPtr:
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// Always hoist the base address of a GetElementPtr.
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if (Idx == 0)
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return 2 * TTI::TCC_Basic;
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return TTI::TCC_Free;
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case Instruction::Store:
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ImmIdx = 0;
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break;
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case Instruction::Add:
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case Instruction::Sub:
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case Instruction::Mul:
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case Instruction::UDiv:
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case Instruction::SDiv:
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case Instruction::URem:
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case Instruction::SRem:
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case Instruction::And:
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case Instruction::Or:
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case Instruction::Xor:
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case Instruction::ICmp:
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ImmIdx = 1;
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break;
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// Always return TCC_Free for the shift value of a shift instruction.
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case Instruction::Shl:
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case Instruction::LShr:
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case Instruction::AShr:
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if (Idx == 1)
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return TTI::TCC_Free;
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break;
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case Instruction::Trunc:
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case Instruction::ZExt:
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case Instruction::SExt:
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case Instruction::IntToPtr:
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case Instruction::PtrToInt:
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case Instruction::BitCast:
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case Instruction::PHI:
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case Instruction::Call:
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case Instruction::Select:
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case Instruction::Ret:
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case Instruction::Load:
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break;
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}
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if (Idx == ImmIdx) {
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unsigned NumConstants = (BitSize + 63) / 64;
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unsigned Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
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return (Cost <= NumConstants * TTI::TCC_Basic)
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? static_cast<unsigned>(TTI::TCC_Free)
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: Cost;
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}
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return AArch64TTIImpl::getIntImmCost(Imm, Ty);
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}
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unsigned AArch64TTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty) {
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assert(Ty->isIntegerTy());
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unsigned BitSize = Ty->getPrimitiveSizeInBits();
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// There is no cost model for constants with a bit size of 0. Return TCC_Free
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// here, so that constant hoisting will ignore this constant.
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if (BitSize == 0)
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return TTI::TCC_Free;
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switch (IID) {
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default:
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return TTI::TCC_Free;
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case Intrinsic::sadd_with_overflow:
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case Intrinsic::uadd_with_overflow:
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case Intrinsic::ssub_with_overflow:
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case Intrinsic::usub_with_overflow:
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case Intrinsic::smul_with_overflow:
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case Intrinsic::umul_with_overflow:
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if (Idx == 1) {
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unsigned NumConstants = (BitSize + 63) / 64;
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unsigned Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
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return (Cost <= NumConstants * TTI::TCC_Basic)
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? static_cast<unsigned>(TTI::TCC_Free)
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: Cost;
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}
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break;
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case Intrinsic::experimental_stackmap:
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if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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case Intrinsic::experimental_patchpoint_void:
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case Intrinsic::experimental_patchpoint_i64:
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if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
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return TTI::TCC_Free;
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break;
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}
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return AArch64TTIImpl::getIntImmCost(Imm, Ty);
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}
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TargetTransformInfo::PopcntSupportKind
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AArch64TTIImpl::getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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if (TyWidth == 32 || TyWidth == 64)
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return TTI::PSK_FastHardware;
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// TODO: AArch64TargetLowering::LowerCTPOP() supports 128bit popcount.
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return TTI::PSK_Software;
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}
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unsigned AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
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Type *Src) {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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assert(ISD && "Invalid opcode");
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EVT SrcTy = TLI->getValueType(Src);
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EVT DstTy = TLI->getValueType(Dst);
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if (!SrcTy.isSimple() || !DstTy.isSimple())
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return BaseT::getCastInstrCost(Opcode, Dst, Src);
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static const TypeConversionCostTblEntry<MVT> ConversionTbl[] = {
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// LowerVectorINT_TO_FP:
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
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// Complex: to v2f32
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
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{ ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 },
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{ ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
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// Complex: to v4f32
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
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{ ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
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{ ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
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// Complex: to v2f64
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
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{ ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
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{ ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
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// LowerVectorFP_TO_INT
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
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// Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
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{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
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{ ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 },
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{ ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f32, 1 },
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// Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2
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{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
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{ ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 2 },
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// Complex, from v2f64: legal type is v2i32, 1 narrowing => ~2.
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{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 },
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{ ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
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{ ISD::FP_TO_UINT, MVT::v2i8, MVT::v2f64, 2 },
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};
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int Idx = ConvertCostTableLookup<MVT>(
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ConversionTbl, array_lengthof(ConversionTbl), ISD, DstTy.getSimpleVT(),
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SrcTy.getSimpleVT());
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if (Idx != -1)
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return ConversionTbl[Idx].Cost;
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return BaseT::getCastInstrCost(Opcode, Dst, Src);
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}
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unsigned AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) {
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assert(Val->isVectorTy() && "This must be a vector type");
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if (Index != -1U) {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
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// This type is legalized to a scalar type.
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if (!LT.second.isVector())
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return 0;
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// The type may be split. Normalize the index to the new type.
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unsigned Width = LT.second.getVectorNumElements();
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Index = Index % Width;
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// The element at index zero is already inside the vector.
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if (Index == 0)
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return 0;
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}
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// All other insert/extracts cost this much.
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return 2;
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}
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unsigned AArch64TTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
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TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo) {
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// Legalize the type.
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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if (ISD == ISD::SDIV &&
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Opd2Info == TargetTransformInfo::OK_UniformConstantValue &&
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Opd2PropInfo == TargetTransformInfo::OP_PowerOf2) {
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// On AArch64, scalar signed division by constants power-of-two are
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// normally expanded to the sequence ADD + CMP + SELECT + SRA.
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// The OperandValue properties many not be same as that of previous
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// operation; conservatively assume OP_None.
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unsigned Cost =
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getArithmeticInstrCost(Instruction::Add, Ty, Opd1Info, Opd2Info,
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TargetTransformInfo::OP_None,
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TargetTransformInfo::OP_None);
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Cost += getArithmeticInstrCost(Instruction::Sub, Ty, Opd1Info, Opd2Info,
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TargetTransformInfo::OP_None,
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TargetTransformInfo::OP_None);
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Cost += getArithmeticInstrCost(Instruction::Select, Ty, Opd1Info, Opd2Info,
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TargetTransformInfo::OP_None,
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TargetTransformInfo::OP_None);
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Cost += getArithmeticInstrCost(Instruction::AShr, Ty, Opd1Info, Opd2Info,
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TargetTransformInfo::OP_None,
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TargetTransformInfo::OP_None);
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return Cost;
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}
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switch (ISD) {
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default:
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return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
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Opd1PropInfo, Opd2PropInfo);
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case ISD::ADD:
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case ISD::MUL:
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case ISD::XOR:
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case ISD::OR:
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case ISD::AND:
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// These nodes are marked as 'custom' for combining purposes only.
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// We know that they are legal. See LowerAdd in ISelLowering.
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return 1 * LT.first;
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}
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}
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unsigned AArch64TTIImpl::getAddressComputationCost(Type *Ty, bool IsComplex) {
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// Address computations in vectorized code with non-consecutive addresses will
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// likely result in more instructions compared to scalar code where the
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// computation can more often be merged into the index mode. The resulting
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// extra micro-ops can significantly decrease throughput.
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unsigned NumVectorInstToHideOverhead = 10;
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if (Ty->isVectorTy() && IsComplex)
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return NumVectorInstToHideOverhead;
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// In many cases the address computation is not merged into the instruction
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// addressing mode.
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return 1;
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}
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unsigned AArch64TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
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Type *CondTy) {
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int ISD = TLI->InstructionOpcodeToISD(Opcode);
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// We don't lower vector selects well that are wider than the register width.
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if (ValTy->isVectorTy() && ISD == ISD::SELECT) {
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// We would need this many instructions to hide the scalarization happening.
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unsigned AmortizationCost = 20;
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static const TypeConversionCostTblEntry<MVT::SimpleValueType>
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VectorSelectTbl[] = {
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{ ISD::SELECT, MVT::v16i1, MVT::v16i16, 16 * AmortizationCost },
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{ ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 * AmortizationCost },
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{ ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 * AmortizationCost },
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{ ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost },
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{ ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
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{ ISD::SELECT, MVT::v16i1, MVT::v16i64, 16 * AmortizationCost }
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};
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EVT SelCondTy = TLI->getValueType(CondTy);
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EVT SelValTy = TLI->getValueType(ValTy);
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if (SelCondTy.isSimple() && SelValTy.isSimple()) {
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int Idx =
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ConvertCostTableLookup(VectorSelectTbl, ISD, SelCondTy.getSimpleVT(),
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SelValTy.getSimpleVT());
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if (Idx != -1)
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return VectorSelectTbl[Idx].Cost;
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}
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}
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return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy);
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}
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unsigned AArch64TTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
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unsigned Alignment,
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unsigned AddressSpace) {
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std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
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if (Opcode == Instruction::Store && Src->isVectorTy() && Alignment != 16 &&
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Src->getVectorElementType()->isIntegerTy(64)) {
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// Unaligned stores are extremely inefficient. We don't split
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// unaligned v2i64 stores because the negative impact that has shown in
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// practice on inlined memcpy code.
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// We make v2i64 stores expensive so that we will only vectorize if there
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// are 6 other instructions getting vectorized.
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unsigned AmortizationCost = 6;
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return LT.first * 2 * AmortizationCost;
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}
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if (Src->isVectorTy() && Src->getVectorElementType()->isIntegerTy(8) &&
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Src->getVectorNumElements() < 8) {
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// We scalarize the loads/stores because there is not v.4b register and we
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// have to promote the elements to v.4h.
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unsigned NumVecElts = Src->getVectorNumElements();
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unsigned NumVectorizableInstsToAmortize = NumVecElts * 2;
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// We generate 2 instructions per vector element.
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return NumVectorizableInstsToAmortize * NumVecElts * 2;
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}
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return LT.first;
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}
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unsigned AArch64TTIImpl::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) {
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unsigned Cost = 0;
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for (auto *I : Tys) {
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if (!I->isVectorTy())
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continue;
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if (I->getScalarSizeInBits() * I->getVectorNumElements() == 128)
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Cost += getMemoryOpCost(Instruction::Store, I, 128, 0) +
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getMemoryOpCost(Instruction::Load, I, 128, 0);
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}
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return Cost;
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}
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unsigned AArch64TTIImpl::getMaxInterleaveFactor() {
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|
if (ST->isCortexA57())
|
|
return 4;
|
|
return 2;
|
|
}
|
|
|
|
void AArch64TTIImpl::getUnrollingPreferences(Loop *L,
|
|
TTI::UnrollingPreferences &UP) {
|
|
// Disable partial & runtime unrolling on -Os.
|
|
UP.PartialOptSizeThreshold = 0;
|
|
}
|
|
|
|
Value *AArch64TTIImpl::getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
|
|
Type *ExpectedType) {
|
|
switch (Inst->getIntrinsicID()) {
|
|
default:
|
|
return nullptr;
|
|
case Intrinsic::aarch64_neon_st2:
|
|
case Intrinsic::aarch64_neon_st3:
|
|
case Intrinsic::aarch64_neon_st4: {
|
|
// Create a struct type
|
|
StructType *ST = dyn_cast<StructType>(ExpectedType);
|
|
if (!ST)
|
|
return nullptr;
|
|
unsigned NumElts = Inst->getNumArgOperands() - 1;
|
|
if (ST->getNumElements() != NumElts)
|
|
return nullptr;
|
|
for (unsigned i = 0, e = NumElts; i != e; ++i) {
|
|
if (Inst->getArgOperand(i)->getType() != ST->getElementType(i))
|
|
return nullptr;
|
|
}
|
|
Value *Res = UndefValue::get(ExpectedType);
|
|
IRBuilder<> Builder(Inst);
|
|
for (unsigned i = 0, e = NumElts; i != e; ++i) {
|
|
Value *L = Inst->getArgOperand(i);
|
|
Res = Builder.CreateInsertValue(Res, L, i);
|
|
}
|
|
return Res;
|
|
}
|
|
case Intrinsic::aarch64_neon_ld2:
|
|
case Intrinsic::aarch64_neon_ld3:
|
|
case Intrinsic::aarch64_neon_ld4:
|
|
if (Inst->getType() == ExpectedType)
|
|
return Inst;
|
|
return nullptr;
|
|
}
|
|
}
|
|
|
|
bool AArch64TTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
|
|
MemIntrinsicInfo &Info) {
|
|
switch (Inst->getIntrinsicID()) {
|
|
default:
|
|
break;
|
|
case Intrinsic::aarch64_neon_ld2:
|
|
case Intrinsic::aarch64_neon_ld3:
|
|
case Intrinsic::aarch64_neon_ld4:
|
|
Info.ReadMem = true;
|
|
Info.WriteMem = false;
|
|
Info.Vol = false;
|
|
Info.NumMemRefs = 1;
|
|
Info.PtrVal = Inst->getArgOperand(0);
|
|
break;
|
|
case Intrinsic::aarch64_neon_st2:
|
|
case Intrinsic::aarch64_neon_st3:
|
|
case Intrinsic::aarch64_neon_st4:
|
|
Info.ReadMem = false;
|
|
Info.WriteMem = true;
|
|
Info.Vol = false;
|
|
Info.NumMemRefs = 1;
|
|
Info.PtrVal = Inst->getArgOperand(Inst->getNumArgOperands() - 1);
|
|
break;
|
|
}
|
|
|
|
switch (Inst->getIntrinsicID()) {
|
|
default:
|
|
return false;
|
|
case Intrinsic::aarch64_neon_ld2:
|
|
case Intrinsic::aarch64_neon_st2:
|
|
Info.MatchingId = VECTOR_LDST_TWO_ELEMENTS;
|
|
break;
|
|
case Intrinsic::aarch64_neon_ld3:
|
|
case Intrinsic::aarch64_neon_st3:
|
|
Info.MatchingId = VECTOR_LDST_THREE_ELEMENTS;
|
|
break;
|
|
case Intrinsic::aarch64_neon_ld4:
|
|
case Intrinsic::aarch64_neon_st4:
|
|
Info.MatchingId = VECTOR_LDST_FOUR_ELEMENTS;
|
|
break;
|
|
}
|
|
return true;
|
|
}
|