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				https://github.com/c64scene-ar/llvm-6502.git
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	This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
		
			
				
	
	
		
			13 lines
		
	
	
		
			342 B
		
	
	
	
		
			LLVM
		
	
	
	
	
	
			
		
		
	
	
			13 lines
		
	
	
		
			342 B
		
	
	
	
		
			LLVM
		
	
	
	
	
	
; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-linux-gnu"
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define i8* @test_call_return_type(i64 %size) {
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entry:
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; CHECK: bl xmalloc
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  %0 = call noalias i8* @xmalloc(i64 undef)
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  ret i8* %0
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}
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declare noalias i8* @xmalloc(i64)
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