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https://github.com/c64scene-ar/llvm-6502.git
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b3275b9fca
Windows on ARM only supports thumb mode execution, so we have to explicitly pick some non-Windows OS to test ARM mode codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208448 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.7 KiB
LLVM
58 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=arm-linux -mcpu=generic | FileCheck %s
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define i32 @uadd_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: uadd_overflow:
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; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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; CHECK: mov r[[R1]], #1
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; CHECK: cmp r[[R2]], r[[R0]]
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; CHECK: movhs r[[R1]], #0
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}
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define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: sadd_overflow:
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; CHECK: add r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]
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; CHECK: mov r[[R1]], #1
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; CHECK: cmp r[[R2]], r[[R0]]
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; CHECK: movvc r[[R1]], #0
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}
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define i32 @usub_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: usub_overflow:
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; CHECK: mov r[[R2]], #1
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; CHECK: cmp r[[R0]], r[[R1]]
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; CHECK: movhs r[[R2]], #0
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}
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define i32 @ssub_overflow(i32 %a, i32 %b) #0 {
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%sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
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%1 = extractvalue { i32, i1 } %sadd, 1
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%2 = zext i1 %1 to i32
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ret i32 %2
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; CHECK-LABEL: ssub_overflow:
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; CHECK: mov r[[R2]], #1
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; CHECK: cmp r[[R0]], r[[R1]]
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; CHECK: movvc r[[R2]], #0
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}
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
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declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2
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declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3
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declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4
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