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19d010b851
The current instruction selection patterns for SMULW[BT] and SMLAW[BT] are incorrect. These instructions multiply a 32-bit and a 16-bit value (both signed) and return the top 32 bits of the 48-bit result. This preserves the 16 bits of overflow, whereas the patterns they currently match truncate the result to 16 bits then sign extend. To select these instructions, we would need to match an ISD::SMUL_LOHI, a sign extend, two shifts and an or. There is no way to match SMUL_LOHI in an instruction pattern as it defines multiple values, so this would have to be done in C++. I have raised http://llvm.org/bugs/show_bug.cgi?id=21297 to cover allowing correct selection of these instructions. This fixes http://llvm.org/bugs/show_bug.cgi?id=19396 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220196 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
697 B
LLVM
27 lines
697 B
LLVM
; RUN: llc -mtriple=arm--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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; We cannot codegen the smulw[bt] or smlaw[bt] instructions for these functions,
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; as the top 16 bits of the result would differ
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define i32 @f1(i32 %a, i16 %b) {
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; CHECK-LABEL: f1:
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; CHECK: mul
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; CHECK: asr
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%tmp1 = sext i16 %b to i32
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%tmp2 = mul i32 %a, %tmp1
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%tmp3 = ashr i32 %tmp2, 16
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ret i32 %tmp3
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}
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define i32 @f2(i32 %a, i16 %b, i32 %c) {
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; CHECK-LABEL: f2:
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; CHECK: mul
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; CHECK: add{{.*}}, asr #16
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%tmp1 = sext i16 %b to i32
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%tmp2 = mul i32 %a, %tmp1
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%tmp3 = ashr i32 %tmp2, 16
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%tmp4 = add i32 %tmp3, %c
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ret i32 %tmp4
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}
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