mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-30 16:17:05 +00:00
1115b2c27e
This is a follow-on patch to: http://reviews.llvm.org/D7093 That patch canonicalized constant splats as build_vectors, and this patch removes the constant check so we can canonicalize all splats as build_vectors. This fixes the 2nd test case in PR22283: http://llvm.org/bugs/show_bug.cgi?id=22283 The unfortunate code duplication between SelectionDAG and DAGCombiner is discussed in the earlier patch review. At least this patch is just removing code... This improves an existing x86 AVX test and changes codegen in an ARM test. Differential Revision: http://reviews.llvm.org/D7389 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229511 91177308-0d34-0410-b5e6-96231b3b80d8
367 lines
12 KiB
LLVM
367 lines
12 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+neon -verify-machineinstrs %s -o - \
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; RUN: | FileCheck %s
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define <8 x i8> @v_dup8(i8 %A) nounwind {
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;CHECK-LABEL: v_dup8:
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;CHECK: vdup.8
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%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
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%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
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%tmp3 = insertelement <8 x i8> %tmp2, i8 %A, i32 2
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%tmp4 = insertelement <8 x i8> %tmp3, i8 %A, i32 3
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%tmp5 = insertelement <8 x i8> %tmp4, i8 %A, i32 4
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%tmp6 = insertelement <8 x i8> %tmp5, i8 %A, i32 5
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%tmp7 = insertelement <8 x i8> %tmp6, i8 %A, i32 6
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%tmp8 = insertelement <8 x i8> %tmp7, i8 %A, i32 7
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ret <8 x i8> %tmp8
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}
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define <4 x i16> @v_dup16(i16 %A) nounwind {
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;CHECK-LABEL: v_dup16:
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;CHECK: vdup.16
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%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
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%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
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%tmp3 = insertelement <4 x i16> %tmp2, i16 %A, i32 2
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%tmp4 = insertelement <4 x i16> %tmp3, i16 %A, i32 3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @v_dup32(i32 %A) nounwind {
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;CHECK-LABEL: v_dup32:
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;CHECK: vdup.32
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%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
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%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
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ret <2 x i32> %tmp2
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}
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define <2 x float> @v_dupfloat(float %A) nounwind {
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;CHECK-LABEL: v_dupfloat:
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;CHECK: vdup.32
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%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
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%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
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ret <2 x float> %tmp2
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}
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define <16 x i8> @v_dupQ8(i8 %A) nounwind {
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;CHECK-LABEL: v_dupQ8:
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;CHECK: vdup.8
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%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
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%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
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%tmp3 = insertelement <16 x i8> %tmp2, i8 %A, i32 2
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%tmp4 = insertelement <16 x i8> %tmp3, i8 %A, i32 3
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%tmp5 = insertelement <16 x i8> %tmp4, i8 %A, i32 4
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%tmp6 = insertelement <16 x i8> %tmp5, i8 %A, i32 5
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%tmp7 = insertelement <16 x i8> %tmp6, i8 %A, i32 6
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%tmp8 = insertelement <16 x i8> %tmp7, i8 %A, i32 7
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%tmp9 = insertelement <16 x i8> %tmp8, i8 %A, i32 8
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%tmp10 = insertelement <16 x i8> %tmp9, i8 %A, i32 9
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%tmp11 = insertelement <16 x i8> %tmp10, i8 %A, i32 10
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%tmp12 = insertelement <16 x i8> %tmp11, i8 %A, i32 11
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%tmp13 = insertelement <16 x i8> %tmp12, i8 %A, i32 12
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%tmp14 = insertelement <16 x i8> %tmp13, i8 %A, i32 13
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%tmp15 = insertelement <16 x i8> %tmp14, i8 %A, i32 14
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%tmp16 = insertelement <16 x i8> %tmp15, i8 %A, i32 15
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ret <16 x i8> %tmp16
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}
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define <8 x i16> @v_dupQ16(i16 %A) nounwind {
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;CHECK-LABEL: v_dupQ16:
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;CHECK: vdup.16
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%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
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%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
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%tmp3 = insertelement <8 x i16> %tmp2, i16 %A, i32 2
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%tmp4 = insertelement <8 x i16> %tmp3, i16 %A, i32 3
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%tmp5 = insertelement <8 x i16> %tmp4, i16 %A, i32 4
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%tmp6 = insertelement <8 x i16> %tmp5, i16 %A, i32 5
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%tmp7 = insertelement <8 x i16> %tmp6, i16 %A, i32 6
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%tmp8 = insertelement <8 x i16> %tmp7, i16 %A, i32 7
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ret <8 x i16> %tmp8
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}
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define <4 x i32> @v_dupQ32(i32 %A) nounwind {
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;CHECK-LABEL: v_dupQ32:
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;CHECK: vdup.32
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%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
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%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
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%tmp3 = insertelement <4 x i32> %tmp2, i32 %A, i32 2
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%tmp4 = insertelement <4 x i32> %tmp3, i32 %A, i32 3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @v_dupQfloat(float %A) nounwind {
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;CHECK-LABEL: v_dupQfloat:
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;CHECK: vdup.32
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%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
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%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
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%tmp3 = insertelement <4 x float> %tmp2, float %A, i32 2
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%tmp4 = insertelement <4 x float> %tmp3, float %A, i32 3
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ret <4 x float> %tmp4
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}
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; Check to make sure it works with shuffles, too.
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define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
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;CHECK-LABEL: v_shuffledup8:
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;CHECK: vdup.8
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%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
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;CHECK-LABEL: v_shuffledup16:
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;CHECK: vdup.16
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%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
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;CHECK-LABEL: v_shuffledup32:
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;CHECK: vdup.32
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%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
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ret <2 x i32> %tmp2
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}
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define <2 x float> @v_shuffledupfloat(float %A) nounwind {
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;CHECK-LABEL: v_shuffledupfloat:
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;CHECK: vdup.32
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%tmp1 = insertelement <2 x float> undef, float %A, i32 0
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
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ret <2 x float> %tmp2
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}
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define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ8:
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;CHECK: vdup.8
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%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
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%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ16:
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;CHECK: vdup.16
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%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
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%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
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;CHECK-LABEL: v_shuffledupQ32:
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;CHECK: vdup.32
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%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
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%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
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ret <4 x i32> %tmp2
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}
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define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
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;CHECK-LABEL: v_shuffledupQfloat:
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;CHECK: vdup.32
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%tmp1 = insertelement <4 x float> undef, float %A, i32 0
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%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
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ret <4 x float> %tmp2
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}
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define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vduplane8:
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;CHECK: vdup.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vduplane16:
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;CHECK: vdup.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vduplane32:
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;CHECK: vdup.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vduplanefloat:
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;CHECK: vdup.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x float> %tmp2
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}
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define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ8:
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;CHECK: vdup.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ16:
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;CHECK: vdup.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vduplaneQ32:
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;CHECK: vdup.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vduplaneQfloat:
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;CHECK: vdup.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x float> %tmp2
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}
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define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x i64> %0
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}
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define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x i64> %0
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}
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define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %0
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}
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define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %0
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}
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; Radar 7373643
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;CHECK-LABEL: redundantVdup:
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;CHECK: vmov.i8
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;CHECK-NOT: vdup.8
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;CHECK: vstr
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define void @redundantVdup(<8 x i8>* %ptr) nounwind {
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%1 = insertelement <8 x i8> undef, i8 -128, i32 0
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%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
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store <8 x i8> %2, <8 x i8>* %ptr, align 8
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ret void
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}
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define <4 x i32> @tdupi(i32 %x, i32 %y) {
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;CHECK-LABEL: tdupi:
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;CHECK: vdup.32
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%1 = insertelement <4 x i32> undef, i32 %x, i32 0
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%2 = insertelement <4 x i32> %1, i32 %x, i32 1
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%3 = insertelement <4 x i32> %2, i32 %x, i32 2
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%4 = insertelement <4 x i32> %3, i32 %y, i32 3
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ret <4 x i32> %4
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}
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define <4 x float> @tdupf(float %x, float %y) {
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;CHECK-LABEL: tdupf:
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;CHECK: vdup.32
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%1 = insertelement <4 x float> undef, float %x, i32 0
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%2 = insertelement <4 x float> %1, float %x, i32 1
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%3 = insertelement <4 x float> %2, float %x, i32 2
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%4 = insertelement <4 x float> %3, float %y, i32 3
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ret <4 x float> %4
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}
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; This test checks that when splatting an element from a vector into another,
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; the value isn't moved out to GPRs first.
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define <4 x i32> @tduplane(<4 x i32> %invec) {
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;CHECK-LABEL: tduplane:
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;CHECK-NOT: vmov {{.*}}, d16[1]
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;CHECK: vdup.32 {{.*}}, d16[1]
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%in = extractelement <4 x i32> %invec, i32 1
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%1 = insertelement <4 x i32> undef, i32 %in, i32 0
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%2 = insertelement <4 x i32> %1, i32 %in, i32 1
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%3 = insertelement <4 x i32> %2, i32 %in, i32 2
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%4 = insertelement <4 x i32> %3, i32 255, i32 3
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ret <4 x i32> %4
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}
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define <2 x float> @check_f32(<4 x float> %v) nounwind {
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;CHECK-LABEL: check_f32:
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;CHECK: vdup.32 {{.*}}, d{{..}}[1]
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%x = extractelement <4 x float> %v, i32 3
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%1 = insertelement <2 x float> undef, float %x, i32 0
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%2 = insertelement <2 x float> %1, float %x, i32 1
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ret <2 x float> %2
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}
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define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
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;CHECK-LABEL: check_i32:
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;CHECK: vdup.32 {{.*}}, d{{..}}[1]
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%x = extractelement <4 x i32> %v, i32 3
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%1 = insertelement <2 x i32> undef, i32 %x, i32 0
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%2 = insertelement <2 x i32> %1, i32 %x, i32 1
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ret <2 x i32> %2
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}
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define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
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;CHECK-LABEL: check_i16:
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;CHECK: vdup.16 {{.*}}, d{{..}}[3]
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%x = extractelement <8 x i16> %v, i32 3
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%1 = insertelement <4 x i16> undef, i16 %x, i32 0
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%2 = insertelement <4 x i16> %1, i16 %x, i32 1
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ret <4 x i16> %2
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}
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define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
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;CHECK-LABEL: check_i8:
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;CHECK: vdup.8 {{.*}}, d{{..}}[3]
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%x = extractelement <16 x i8> %v, i32 3
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%1 = insertelement <8 x i8> undef, i8 %x, i32 0
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%2 = insertelement <8 x i8> %1, i8 %x, i32 1
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ret <8 x i8> %2
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}
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; Check that an SPR splat produces a vdup.
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define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) {
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;CHECK-LABEL: check_spr_splat2:
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;CHECK: vdup.32 d
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%conv = sitofp i16 %q to float
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%splat.splatinsert = insertelement <2 x float> undef, float %conv, i32 0
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%splat.splat = shufflevector <2 x float> %splat.splatinsert, <2 x float> undef, <2 x i32> zeroinitializer
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%sub = fsub <2 x float> %splat.splat, %p
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ret <2 x float> %sub
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}
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define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) {
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;CHECK-LABEL: check_spr_splat4:
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;CHECK: vld1.16
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%conv = sitofp i16 %q to float
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%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
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%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
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%sub = fsub <4 x float> %splat.splat, %p
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ret <4 x float> %sub
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}
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; Same codegen as above test; scalar is splatted using vld1, so shuffle index is irrelevant.
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define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) {
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;CHECK-LABEL: check_spr_splat4_lane1:
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;CHECK: vld1.16
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%conv = sitofp i16 %q to float
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%splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
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%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%sub = fsub <4 x float> %splat.splat, %p
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ret <4 x float> %sub
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}
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