mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
7eedd07d5e
Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8
189 lines
6.8 KiB
LLVM
189 lines
6.8 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP32 \
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; RUN: -check-prefix=M2
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP32 \
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; RUN: -check-prefix=32R1-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP32 \
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; RUN: -check-prefix=32R1-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP32 \
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; RUN: -check-prefix=32R1-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP32 \
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; RUN: -check-prefix=32R1-R5
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP32 \
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; RUN: -check-prefix=32R6
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP64 \
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; RUN: -check-prefix=M3
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP64 \
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; RUN: -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP64 \
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; RUN: -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP64 \
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; RUN: -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP64 \
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; RUN: -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP64 \
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; RUN: -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=GP64 \
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; RUN: -check-prefix=64R6
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define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
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entry:
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; ALL-LABEL: lshr_i1:
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; ALL: move $2, $4
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%r = lshr i1 %a, %b
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ret i1 %r
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}
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define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
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entry:
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; ALL-LABEL: lshr_i8:
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; ALL: srlv $[[T0:[0-9]+]], $4, $5
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; ALL: andi $2, $[[T0]], 255
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%r = lshr i8 %a, %b
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ret i8 %r
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}
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define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
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entry:
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; ALL-LABEL: lshr_i16:
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; ALL: srlv $[[T0:[0-9]+]], $4, $5
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; ALL: andi $2, $[[T0]], 65535
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%r = lshr i16 %a, %b
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ret i16 %r
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}
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define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
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entry:
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; ALL-LABEL: lshr_i32:
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; ALL: srlv $2, $4, $5
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%r = lshr i32 %a, %b
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ret i32 %r
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}
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define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) {
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entry:
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; ALL-LABEL: lshr_i64:
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; M2: srlv $[[T0:[0-9]+]], $4, $7
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; M2: andi $[[T1:[0-9]+]], $7, 32
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; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
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; M2: move $3, $[[T0]]
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; M2: srlv $[[T2:[0-9]+]], $5, $7
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; M2: not $[[T3:[0-9]+]], $7
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; M2: sll $[[T4:[0-9]+]], $4, 1
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; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
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; M2: or $3, $[[T3]], $[[T2]]
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; M2: $[[BB0]]:
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; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]]
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; M2: addiu $2, $zero, 0
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; M2: move $2, $[[T0]]
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; M2: $[[BB1]]:
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; M2: jr $ra
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; M2: nop
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; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
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; 32R1-R5: not $[[T1:[0-9]+]], $7
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; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
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; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; 32R1-R5: or $3, $[[T3]], $[[T0]]
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; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7
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; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
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; 32R1-R5: movn $3, $[[T4]], $[[T5]]
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; 32R1-R5: jr $ra
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; 32R1-R5: movn $2, $zero, $[[T5]]
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; 32R6: srlv $[[T0:[0-9]+]], $5, $7
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; 32R6: not $[[T1:[0-9]+]], $7
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; 32R6: sll $[[T2:[0-9]+]], $4, 1
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; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
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; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]]
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; 32R6: andi $[[T5:[0-9]+]], $7, 32
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; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]]
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; 32R6: srlv $[[T7:[0-9]+]], $4, $7
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; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]]
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; 32R6: or $3, $[[T8]], $[[T6]]
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; 32R6: jr $ra
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; 32R6: seleqz $2, $[[T7]], $[[T5]]
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; GP64: sll $[[T0:[0-9]+]], $5, 0
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; GP64: dsrlv $2, $4, $[[T0]]
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%r = lshr i64 %a, %b
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ret i64 %r
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}
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define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: lshr_i128:
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; GP32: lw $25, %call16(__lshrti3)($gp)
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; M3: sll $[[T0:[0-9]+]], $7, 0
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; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]]
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; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
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; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
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; M3: move $3, $[[T1]]
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; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
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; M3: dsll $[[T5:[0-9]+]], $4, 1
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; M3: not $[[T6:[0-9]+]], $[[T0]]
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; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
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; M3: or $3, $[[T7]], $[[T4]]
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; M3: $[[BB0]]:
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; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
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; M3: daddiu $2, $zero, 0
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; M3: move $2, $[[T1]]
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; M3: $[[BB1]]:
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; M3: jr $ra
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; M3: nop
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; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
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; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
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; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1
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; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
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; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
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; GP64-NOT-R6: dsrlv $2, $4, $[[T0]]
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; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32
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; GP64-NOT-R6: movn $3, $2, $[[T5]]
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; GP64-NOT-R6: jr $ra
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; GP64-NOT-R6: movn $2, $zero, $1
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; 64R6: sll $[[T0:[0-9]+]], $7, 0
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; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
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; 64R6: dsll $[[T2:[0-9]+]], $4, 1
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; 64R6: not $[[T3:[0-9]+]], $[[T0]]
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; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
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; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]]
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; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32
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; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
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; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
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; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]]
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; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
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; 64R6: or $3, $[[T10]], $[[T8]]
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; 64R6: jr $ra
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; 64R6: seleqz $2, $[[T0]], $[[T7]]
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%r = lshr i128 %a, %b
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ret i128 %r
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}
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