mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-10-31 08:16:47 +00:00
7eedd07d5e
Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8
117 lines
3.3 KiB
LLVM
117 lines
3.3 KiB
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=R6 -check-prefix=GP32
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; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
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; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=R6 -check-prefix=64R6
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define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
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entry:
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; ALL-LABEL: udiv_i1:
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; NOT-R6: divu $zero, $4, $5
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; NOT-R6: teq $5, $zero, 7
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; NOT-R6: mflo $2
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; R6: divu $2, $4, $5
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; R6: teq $5, $zero, 7
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%r = udiv i1 %a, %b
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ret i1 %r
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}
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define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
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entry:
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; ALL-LABEL: udiv_i8:
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; NOT-R6: divu $zero, $4, $5
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; NOT-R6: teq $5, $zero, 7
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; NOT-R6: mflo $2
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; R6: divu $2, $4, $5
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; R6: teq $5, $zero, 7
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%r = udiv i8 %a, %b
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ret i8 %r
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}
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define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
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entry:
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; ALL-LABEL: udiv_i16:
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; NOT-R6: divu $zero, $4, $5
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; NOT-R6: teq $5, $zero, 7
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; NOT-R6: mflo $2
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; R6: divu $2, $4, $5
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; R6: teq $5, $zero, 7
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%r = udiv i16 %a, %b
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ret i16 %r
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}
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define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
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entry:
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; ALL-LABEL: udiv_i32:
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; NOT-R6: divu $zero, $4, $5
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; NOT-R6: teq $5, $zero, 7
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; NOT-R6: mflo $2
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; R6: divu $2, $4, $5
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; R6: teq $5, $zero, 7
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%r = udiv i32 %a, %b
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ret i32 %r
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}
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define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
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entry:
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; ALL-LABEL: udiv_i64:
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; GP32: lw $25, %call16(__udivdi3)($gp)
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; GP64-NOT-R6: ddivu $zero, $4, $5
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; GP64-NOT-R6: teq $5, $zero, 7
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; GP64-NOT-R6: mflo $2
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; 64R6: ddivu $2, $4, $5
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; 64R6: teq $5, $zero, 7
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%r = udiv i64 %a, %b
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ret i64 %r
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}
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define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
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entry:
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; ALL-LABEL: udiv_i128:
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; GP32: lw $25, %call16(__udivti3)($gp)
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; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp)
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; 64-R6: ld $25, %call16(__udivti3)($gp)
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%r = udiv i128 %a, %b
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ret i128 %r
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}
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