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https://github.com/c64scene-ar/llvm-6502.git
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48dfa127d7
Summary: I had forgotten to check for NotSlowIncDec in the patterns that can generate inc/dec for the above pattern (added in D4796). This currently applies to Atom Silvermont, KNL and SKX. Test Plan: New checks on atomic_mi.ll Reviewers: jfb, nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5677 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219336 91177308-0d34-0410-b5e6-96231b3b80d8
526 lines
12 KiB
LLVM
526 lines
12 KiB
LLVM
; RUN: llc < %s -march=x86-64 -verify-machineinstrs | FileCheck %s --check-prefix X64
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; RUN: llc < %s -march=x86 -verify-machineinstrs | FileCheck %s --check-prefix X32
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; RUN: llc < %s -march=x86-64 -mattr=slow-incdec -verify-machineinstrs | FileCheck %s --check-prefix SLOW_INC
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; This file checks that atomic (non-seq_cst) stores of immediate values are
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; done in one mov instruction and not 2. More precisely, it makes sure that the
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; immediate is not first copied uselessly into a register.
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; Similarily, it checks that a binary operation of an immediate with an atomic
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; variable that is stored back in that variable is done as a single instruction.
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; For example: x.store(42 + x.load(memory_order_acquire), memory_order_release)
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; should be just an add instruction, instead of loading x into a register, doing
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; an add and storing the result back.
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; The binary operations supported are currently add, and, or, xor.
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; sub is not supported because they are translated by an addition of the
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; negated immediate.
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; Finally, we also check the same kind of pattern for inc/dec
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; seq_cst stores are left as (lock) xchgl, but we try to check every other
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; attribute at least once.
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; Please note that these operations do not require the lock prefix: only
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; sequentially consistent stores require this kind of protection on X86.
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; And even for seq_cst operations, llvm uses the xchg instruction which has
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; an implicit lock prefix, so making it explicit is not required.
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define void @store_atomic_imm_8(i8* %p) {
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; X64-LABEL: store_atomic_imm_8
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; X64: movb
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; X64-NOT: movb
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; X32-LABEL: store_atomic_imm_8
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; X32: movb
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; X32-NOT: movb
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store atomic i8 42, i8* %p release, align 1
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ret void
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}
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define void @store_atomic_imm_16(i16* %p) {
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; X64-LABEL: store_atomic_imm_16
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; X64: movw
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; X64-NOT: movw
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; X32-LABEL: store_atomic_imm_16
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; X32: movw
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; X32-NOT: movw
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store atomic i16 42, i16* %p monotonic, align 2
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ret void
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}
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define void @store_atomic_imm_32(i32* %p) {
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; X64-LABEL: store_atomic_imm_32
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; X64: movl
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; X64-NOT: movl
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; On 32 bits, there is an extra movl for each of those functions
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; (probably for alignment reasons).
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; X32-LABEL: store_atomic_imm_32
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; X32: movl 4(%esp), %eax
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; X32: movl
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; X32-NOT: movl
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store atomic i32 42, i32* %p release, align 4
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ret void
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}
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define void @store_atomic_imm_64(i64* %p) {
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; X64-LABEL: store_atomic_imm_64
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; X64: movq
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; X64-NOT: movq
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; These are implemented with a CAS loop on 32 bit architectures, and thus
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; cannot be optimized in the same way as the others.
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; X32-LABEL: store_atomic_imm_64
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; X32: cmpxchg8b
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store atomic i64 42, i64* %p release, align 8
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ret void
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}
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; If an immediate is too big to fit in 32 bits, it cannot be store in one mov,
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; even on X64, one must use movabsq that can only target a register.
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define void @store_atomic_imm_64_big(i64* %p) {
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; X64-LABEL: store_atomic_imm_64_big
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; X64: movabsq
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; X64: movq
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store atomic i64 100000000000, i64* %p monotonic, align 8
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ret void
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}
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; It would be incorrect to replace a lock xchgl by a movl
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define void @store_atomic_imm_32_seq_cst(i32* %p) {
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; X64-LABEL: store_atomic_imm_32_seq_cst
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; X64: xchgl
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; X32-LABEL: store_atomic_imm_32_seq_cst
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; X32: xchgl
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store atomic i32 42, i32* %p seq_cst, align 4
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ret void
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}
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; ----- ADD -----
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define void @add_8(i8* %p) {
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; X64-LABEL: add_8
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; X64-NOT: lock
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; X64: addb
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; X64-NOT: movb
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; X32-LABEL: add_8
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; X32-NOT: lock
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; X32: addb
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; X32-NOT: movb
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%1 = load atomic i8* %p seq_cst, align 1
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%2 = add i8 %1, 2
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @add_16(i16* %p) {
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; Currently the transformation is not done on 16 bit accesses, as the backend
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; treat 16 bit arithmetic as expensive on X86/X86_64.
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; X64-LABEL: add_16
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; X64-NOT: addw
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; X32-LABEL: add_16
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; X32-NOT: addw
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%1 = load atomic i16* %p acquire, align 2
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%2 = add i16 %1, 2
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store atomic i16 %2, i16* %p release, align 2
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ret void
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}
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define void @add_32(i32* %p) {
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; X64-LABEL: add_32
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; X64-NOT: lock
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; X64: addl
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; X64-NOT: movl
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; X32-LABEL: add_32
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; X32-NOT: lock
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; X32: addl
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; X32-NOT: movl
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%1 = load atomic i32* %p acquire, align 4
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%2 = add i32 %1, 2
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store atomic i32 %2, i32* %p monotonic, align 4
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ret void
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}
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define void @add_64(i64* %p) {
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; X64-LABEL: add_64
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; X64-NOT: lock
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; X64: addq
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; X64-NOT: movq
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; We do not check X86-32 as it cannot do 'addq'.
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; X32-LABEL: add_64
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%1 = load atomic i64* %p acquire, align 8
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%2 = add i64 %1, 2
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store atomic i64 %2, i64* %p release, align 8
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ret void
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}
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define void @add_32_seq_cst(i32* %p) {
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; X64-LABEL: add_32_seq_cst
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; X64: xchgl
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; X32-LABEL: add_32_seq_cst
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; X32: xchgl
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%1 = load atomic i32* %p monotonic, align 4
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%2 = add i32 %1, 2
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store atomic i32 %2, i32* %p seq_cst, align 4
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ret void
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}
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; ----- AND -----
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define void @and_8(i8* %p) {
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; X64-LABEL: and_8
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; X64-NOT: lock
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; X64: andb
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; X64-NOT: movb
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; X32-LABEL: and_8
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; X32-NOT: lock
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; X32: andb
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; X32-NOT: movb
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%1 = load atomic i8* %p monotonic, align 1
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%2 = and i8 %1, 2
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @and_16(i16* %p) {
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; Currently the transformation is not done on 16 bit accesses, as the backend
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; treat 16 bit arithmetic as expensive on X86/X86_64.
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; X64-LABEL: and_16
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; X64-NOT: andw
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; X32-LABEL: and_16
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; X32-NOT: andw
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%1 = load atomic i16* %p acquire, align 2
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%2 = and i16 %1, 2
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store atomic i16 %2, i16* %p release, align 2
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ret void
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}
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define void @and_32(i32* %p) {
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; X64-LABEL: and_32
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; X64-NOT: lock
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; X64: andl
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; X64-NOT: movl
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; X32-LABEL: and_32
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; X32-NOT: lock
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; X32: andl
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; X32-NOT: movl
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%1 = load atomic i32* %p acquire, align 4
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%2 = and i32 %1, 2
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store atomic i32 %2, i32* %p release, align 4
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ret void
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}
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define void @and_64(i64* %p) {
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; X64-LABEL: and_64
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; X64-NOT: lock
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; X64: andq
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; X64-NOT: movq
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; We do not check X86-32 as it cannot do 'andq'.
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; X32-LABEL: and_64
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%1 = load atomic i64* %p acquire, align 8
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%2 = and i64 %1, 2
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store atomic i64 %2, i64* %p release, align 8
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ret void
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}
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define void @and_32_seq_cst(i32* %p) {
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; X64-LABEL: and_32_seq_cst
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; X64: xchgl
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; X32-LABEL: and_32_seq_cst
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; X32: xchgl
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%1 = load atomic i32* %p monotonic, align 4
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%2 = and i32 %1, 2
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store atomic i32 %2, i32* %p seq_cst, align 4
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ret void
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}
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; ----- OR -----
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define void @or_8(i8* %p) {
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; X64-LABEL: or_8
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; X64-NOT: lock
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; X64: orb
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; X64-NOT: movb
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; X32-LABEL: or_8
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; X32-NOT: lock
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; X32: orb
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; X32-NOT: movb
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%1 = load atomic i8* %p acquire, align 1
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%2 = or i8 %1, 2
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @or_16(i16* %p) {
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; X64-LABEL: or_16
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; X64-NOT: orw
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; X32-LABEL: or_16
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; X32-NOT: orw
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%1 = load atomic i16* %p acquire, align 2
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%2 = or i16 %1, 2
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store atomic i16 %2, i16* %p release, align 2
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ret void
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}
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define void @or_32(i32* %p) {
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; X64-LABEL: or_32
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; X64-NOT: lock
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; X64: orl
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; X64-NOT: movl
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; X32-LABEL: or_32
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; X32-NOT: lock
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; X32: orl
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; X32-NOT: movl
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%1 = load atomic i32* %p acquire, align 4
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%2 = or i32 %1, 2
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store atomic i32 %2, i32* %p release, align 4
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ret void
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}
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define void @or_64(i64* %p) {
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; X64-LABEL: or_64
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; X64-NOT: lock
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; X64: orq
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; X64-NOT: movq
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; We do not check X86-32 as it cannot do 'orq'.
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; X32-LABEL: or_64
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%1 = load atomic i64* %p acquire, align 8
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%2 = or i64 %1, 2
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store atomic i64 %2, i64* %p release, align 8
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ret void
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}
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define void @or_32_seq_cst(i32* %p) {
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; X64-LABEL: or_32_seq_cst
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; X64: xchgl
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; X32-LABEL: or_32_seq_cst
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; X32: xchgl
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%1 = load atomic i32* %p monotonic, align 4
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%2 = or i32 %1, 2
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store atomic i32 %2, i32* %p seq_cst, align 4
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ret void
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}
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; ----- XOR -----
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define void @xor_8(i8* %p) {
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; X64-LABEL: xor_8
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; X64-NOT: lock
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; X64: xorb
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; X64-NOT: movb
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; X32-LABEL: xor_8
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; X32-NOT: lock
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; X32: xorb
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; X32-NOT: movb
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%1 = load atomic i8* %p acquire, align 1
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%2 = xor i8 %1, 2
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @xor_16(i16* %p) {
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; X64-LABEL: xor_16
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; X64-NOT: xorw
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; X32-LABEL: xor_16
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; X32-NOT: xorw
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%1 = load atomic i16* %p acquire, align 2
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%2 = xor i16 %1, 2
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store atomic i16 %2, i16* %p release, align 2
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ret void
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}
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define void @xor_32(i32* %p) {
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; X64-LABEL: xor_32
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; X64-NOT: lock
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; X64: xorl
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; X64-NOT: movl
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; X32-LABEL: xor_32
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; X32-NOT: lock
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; X32: xorl
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; X32-NOT: movl
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%1 = load atomic i32* %p acquire, align 4
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%2 = xor i32 %1, 2
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store atomic i32 %2, i32* %p release, align 4
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ret void
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}
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define void @xor_64(i64* %p) {
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; X64-LABEL: xor_64
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; X64-NOT: lock
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; X64: xorq
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; X64-NOT: movq
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; We do not check X86-32 as it cannot do 'xorq'.
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; X32-LABEL: xor_64
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%1 = load atomic i64* %p acquire, align 8
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%2 = xor i64 %1, 2
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store atomic i64 %2, i64* %p release, align 8
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ret void
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}
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define void @xor_32_seq_cst(i32* %p) {
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; X64-LABEL: xor_32_seq_cst
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; X64: xchgl
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; X32-LABEL: xor_32_seq_cst
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; X32: xchgl
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%1 = load atomic i32* %p monotonic, align 4
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%2 = xor i32 %1, 2
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store atomic i32 %2, i32* %p seq_cst, align 4
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ret void
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}
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; ----- INC -----
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define void @inc_8(i8* %p) {
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; X64-LABEL: inc_8
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; X64-NOT: lock
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; X64: incb
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; X64-NOT: movb
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; X32-LABEL: inc_8
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; X32-NOT: lock
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; X32: incb
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; X32-NOT: movb
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; SLOW_INC-LABEL: inc_8
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; SLOW_INC-NOT: incb
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; SLOW_INC-NOT: movb
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%1 = load atomic i8* %p seq_cst, align 1
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%2 = add i8 %1, 1
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @inc_16(i16* %p) {
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; Currently the transformation is not done on 16 bit accesses, as the backend
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; treat 16 bit arithmetic as expensive on X86/X86_64.
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; X64-LABEL: inc_16
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; X64-NOT: incw
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; X32-LABEL: inc_16
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; X32-NOT: incw
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; SLOW_INC-LABEL: inc_16
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; SLOW_INC-NOT: incw
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%1 = load atomic i16* %p acquire, align 2
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%2 = add i16 %1, 1
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store atomic i16 %2, i16* %p release, align 2
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ret void
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}
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define void @inc_32(i32* %p) {
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; X64-LABEL: inc_32
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; X64-NOT: lock
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; X64: incl
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; X64-NOT: movl
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; X32-LABEL: inc_32
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; X32-NOT: lock
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; X32: incl
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; X32-NOT: movl
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; SLOW_INC-LABEL: inc_32
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; SLOW_INC-NOT: incl
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; SLOW_INC-NOT: movl
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%1 = load atomic i32* %p acquire, align 4
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%2 = add i32 %1, 1
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store atomic i32 %2, i32* %p monotonic, align 4
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ret void
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}
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define void @inc_64(i64* %p) {
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; X64-LABEL: inc_64
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; X64-NOT: lock
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; X64: incq
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; X64-NOT: movq
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; We do not check X86-32 as it cannot do 'incq'.
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; X32-LABEL: inc_64
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; SLOW_INC-LABEL: inc_64
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; SLOW_INC-NOT: incq
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; SLOW_INC-NOT: movq
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%1 = load atomic i64* %p acquire, align 8
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%2 = add i64 %1, 1
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store atomic i64 %2, i64* %p release, align 8
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ret void
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}
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define void @inc_32_seq_cst(i32* %p) {
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; X64-LABEL: inc_32_seq_cst
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; X64: xchgl
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; X32-LABEL: inc_32_seq_cst
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; X32: xchgl
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%1 = load atomic i32* %p monotonic, align 4
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%2 = add i32 %1, 1
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store atomic i32 %2, i32* %p seq_cst, align 4
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ret void
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}
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; ----- DEC -----
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define void @dec_8(i8* %p) {
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; X64-LABEL: dec_8
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; X64-NOT: lock
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; X64: decb
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; X64-NOT: movb
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; X32-LABEL: dec_8
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; X32-NOT: lock
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; X32: decb
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; X32-NOT: movb
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; SLOW_INC-LABEL: dec_8
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; SLOW_INC-NOT: decb
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; SLOW_INC-NOT: movb
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%1 = load atomic i8* %p seq_cst, align 1
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%2 = sub i8 %1, 1
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @dec_16(i16* %p) {
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; Currently the transformation is not done on 16 bit accesses, as the backend
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; treat 16 bit arithmetic as expensive on X86/X86_64.
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; X64-LABEL: dec_16
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; X64-NOT: decw
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; X32-LABEL: dec_16
|
|
; X32-NOT: decw
|
|
; SLOW_INC-LABEL: dec_16
|
|
; SLOW_INC-NOT: decw
|
|
%1 = load atomic i16* %p acquire, align 2
|
|
%2 = sub i16 %1, 1
|
|
store atomic i16 %2, i16* %p release, align 2
|
|
ret void
|
|
}
|
|
|
|
define void @dec_32(i32* %p) {
|
|
; X64-LABEL: dec_32
|
|
; X64-NOT: lock
|
|
; X64: decl
|
|
; X64-NOT: movl
|
|
; X32-LABEL: dec_32
|
|
; X32-NOT: lock
|
|
; X32: decl
|
|
; X32-NOT: movl
|
|
; SLOW_INC-LABEL: dec_32
|
|
; SLOW_INC-NOT: decl
|
|
; SLOW_INC-NOT: movl
|
|
%1 = load atomic i32* %p acquire, align 4
|
|
%2 = sub i32 %1, 1
|
|
store atomic i32 %2, i32* %p monotonic, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @dec_64(i64* %p) {
|
|
; X64-LABEL: dec_64
|
|
; X64-NOT: lock
|
|
; X64: decq
|
|
; X64-NOT: movq
|
|
; We do not check X86-32 as it cannot do 'decq'.
|
|
; X32-LABEL: dec_64
|
|
; SLOW_INC-LABEL: dec_64
|
|
; SLOW_INC-NOT: decq
|
|
; SLOW_INC-NOT: movq
|
|
%1 = load atomic i64* %p acquire, align 8
|
|
%2 = sub i64 %1, 1
|
|
store atomic i64 %2, i64* %p release, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @dec_32_seq_cst(i32* %p) {
|
|
; X64-LABEL: dec_32_seq_cst
|
|
; X64: xchgl
|
|
; X32-LABEL: dec_32_seq_cst
|
|
; X32: xchgl
|
|
%1 = load atomic i32* %p monotonic, align 4
|
|
%2 = sub i32 %1, 1
|
|
store atomic i32 %2, i32* %p seq_cst, align 4
|
|
ret void
|
|
}
|