mirror of
https://github.com/c64scene-ar/llvm-6502.git
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04715c9915
Implement a BITCAST dag combine to transform i32->mmx conversion patterns into a X86 specific node (MMX_MOVW2D) and guarantee that moves between i32 and x86mmx are better handled, i.e., don't use store-load to do the conversion.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228293 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.3 KiB
LLVM
79 lines
2.3 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-darwin -x86-experimental-vector-widening-legalization -mattr=+mmx,+sse2 | FileCheck %s
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define i32 @t0(i64 %x) {
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; CHECK-LABEL: t0:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: movd %rdi, %mm0
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; CHECK-NEXT: pshufw $238, %mm0, %mm0
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; CHECK-NEXT: movd %mm0, %eax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast i64 %x to <4 x i16>
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%1 = bitcast <4 x i16> %0 to x86_mmx
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%2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -18)
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%3 = bitcast x86_mmx %2 to <4 x i16>
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%4 = bitcast <4 x i16> %3 to <1 x i64>
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%5 = extractelement <1 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <2 x i32>
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%7 = extractelement <2 x i32> %6, i32 0
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ret i32 %7
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}
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define i64 @t1(i64 %x, i32 %n) {
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; CHECK-LABEL: t1:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: movd %esi, %mm0
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; CHECK-NEXT: movd %rdi, %mm1
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; CHECK-NEXT: psllq %mm0, %mm1
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; CHECK-NEXT: movd %mm1, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast i64 %x to x86_mmx
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%1 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %0, i32 %n)
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%2 = bitcast x86_mmx %1 to i64
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ret i64 %2
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}
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define i64 @t2(i64 %x, i32 %n, i32 %w) {
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; CHECK-LABEL: t2:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: movd %esi, %mm0
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; CHECK-NEXT: movd %edx, %mm1
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; CHECK-NEXT: psllq %mm0, %mm1
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; CHECK-NEXT: movd %rdi, %mm0
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; CHECK-NEXT: por %mm1, %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = insertelement <2 x i32> undef, i32 %w, i32 0
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%1 = insertelement <2 x i32> %0, i32 0, i32 1
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%2 = bitcast <2 x i32> %1 to x86_mmx
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%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %2, i32 %n)
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%4 = bitcast i64 %x to x86_mmx
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%5 = tail call x86_mmx @llvm.x86.mmx.por(x86_mmx %4, x86_mmx %3)
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%6 = bitcast x86_mmx %5 to i64
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ret i64 %6
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}
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define i64 @t3(<1 x i64>* %y, i32* %n) {
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; CHECK-LABEL: t3:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: movd (%rsi), %mm1
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; CHECK-NEXT: psllq %mm1, %mm0
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; CHECK-NEXT: movd %mm0, %rax
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <1 x i64>* %y to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = load i32* %n, align 4
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%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
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%4 = bitcast x86_mmx %3 to i64
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ret i64 %4
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}
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declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
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declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32)
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declare x86_mmx @llvm.x86.mmx.por(x86_mmx, x86_mmx)
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