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https://github.com/c64scene-ar/llvm-6502.git
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5f4e6e1ec0
Optimize the select instructions sequence to use the EFLAGS directly from a compare when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211543 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
1.8 KiB
LLVM
63 lines
1.8 KiB
LLVM
; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s
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; Test conditional move for the supported types (i16, i32, and i32) and
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; conditon input (argument or cmp). Currently i8 is not supported.
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define zeroext i16 @select_cmov_i16(i1 zeroext %cond, i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: select_cmov_i16
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; CHECK: testb $1, %dil
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; CHECK-NEXT: cmovew %dx, %si
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; CHECK-NEXT: movzwl %si, %eax
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%1 = select i1 %cond, i16 %a, i16 %b
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ret i16 %1
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}
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define zeroext i16 @select_cmp_cmov_i16(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: select_cmp_cmov_i16
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; CHECK: cmpw %si, %di
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; CHECK-NEXT: cmovbw %di, %si
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; CHECK-NEXT: movzwl %si, %eax
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%1 = icmp ult i16 %a, %b
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%2 = select i1 %1, i16 %a, i16 %b
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ret i16 %2
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}
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define i32 @select_cmov_i32(i1 zeroext %cond, i32 %a, i32 %b) {
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; CHECK-LABEL: select_cmov_i32
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; CHECK: testb $1, %dil
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; CHECK-NEXT: cmovel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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%1 = select i1 %cond, i32 %a, i32 %b
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ret i32 %1
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}
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define i32 @select_cmp_cmov_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: select_cmp_cmov_i32
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; CHECK: cmpl %esi, %edi
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; CHECK-NEXT: cmovbl %edi, %esi
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; CHECK-NEXT: movl %esi, %eax
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%1 = icmp ult i32 %a, %b
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%2 = select i1 %1, i32 %a, i32 %b
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ret i32 %2
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}
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define i64 @select_cmov_i64(i1 zeroext %cond, i64 %a, i64 %b) {
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; CHECK-LABEL: select_cmov_i64
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; CHECK: testb $1, %dil
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; CHECK-NEXT: cmoveq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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%1 = select i1 %cond, i64 %a, i64 %b
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ret i64 %1
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}
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define i64 @select_cmp_cmov_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: select_cmp_cmov_i64
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: cmovbq %rdi, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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%1 = icmp ult i64 %a, %b
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%2 = select i1 %1, i64 %a, i64 %b
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ret i64 %2
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}
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