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https://github.com/c64scene-ar/llvm-6502.git
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34288d885e
Now that we can fully specify extload legality, we can declare them legal for the PMOVSX/PMOVZX instructions. This for instance enables a DAGCombine to fire on code such as (and (<zextload-equivalent> ...), <redundant mask>) to turn it into: (zextload ...) as seen in the testcase changes. There is one regression, in widen_load-2.ll: we're no longer able to do store-to-load forwarding with illegal extload memory types. This will be addressed separately. Differential Revision: http://reviews.llvm.org/D6533 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226676 91177308-0d34-0410-b5e6-96231b3b80d8
136 lines
3.0 KiB
LLVM
136 lines
3.0 KiB
LLVM
; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7 | FileCheck %s
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; RUN: opt -instsimplify -disable-output < %s
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;CHECK: SHUFF0
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define <8 x i32*> @SHUFF0(<4 x i32*> %ptrv) nounwind {
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entry:
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%G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <8 x i32> <i32 2, i32 7, i32 1, i32 2, i32 4, i32 5, i32 1, i32 1>
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;CHECK: pshufd
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ret <8 x i32*> %G
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;CHECK: ret
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}
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;CHECK: SHUFF1
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define <4 x i32*> @SHUFF1(<4 x i32*> %ptrv) nounwind {
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entry:
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%G = shufflevector <4 x i32*> %ptrv, <4 x i32*> %ptrv, <4 x i32> <i32 2, i32 7, i32 7, i32 2>
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;CHECK: pshufd
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ret <4 x i32*> %G
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;CHECK: ret
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}
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;CHECK: SHUFF3
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define <4 x i8*> @SHUFF3(<4 x i8*> %ptrv) nounwind {
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entry:
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%G = shufflevector <4 x i8*> %ptrv, <4 x i8*> undef, <4 x i32> <i32 2, i32 7, i32 1, i32 2>
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;CHECK: pshufd
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ret <4 x i8*> %G
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;CHECK: ret
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}
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;CHECK: LOAD0
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define <4 x i8*> @LOAD0(<4 x i8*>* %p) nounwind {
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entry:
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%G = load <4 x i8*>* %p
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;CHECK: movaps
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ret <4 x i8*> %G
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;CHECK: ret
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}
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;CHECK: LOAD1
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define <4 x i8*> @LOAD1(<4 x i8*>* %p) nounwind {
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entry:
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%G = load <4 x i8*>* %p
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;CHECK: movdqa
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;CHECK: pshufd
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;CHECK: movdqa
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%T = shufflevector <4 x i8*> %G, <4 x i8*> %G, <4 x i32> <i32 7, i32 1, i32 4, i32 3>
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store <4 x i8*> %T, <4 x i8*>* %p
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ret <4 x i8*> %G
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;CHECK: ret
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}
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;CHECK: LOAD2
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define <4 x i8*> @LOAD2(<4 x i8*>* %p) nounwind {
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entry:
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%I = alloca <4 x i8*>
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;CHECK: sub
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%G = load <4 x i8*>* %p
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;CHECK: movaps
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store <4 x i8*> %G, <4 x i8*>* %I
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;CHECK: movaps
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%Z = load <4 x i8*>* %I
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ret <4 x i8*> %Z
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;CHECK: add
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;CHECK: ret
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}
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;CHECK: INT2PTR0
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define <4 x i32> @INT2PTR0(<4 x i8*>* %p) nounwind {
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entry:
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%G = load <4 x i8*>* %p
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;CHECK: movl
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;CHECK: movaps
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%K = ptrtoint <4 x i8*> %G to <4 x i32>
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;CHECK: ret
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ret <4 x i32> %K
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}
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;CHECK: INT2PTR1
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define <4 x i32*> @INT2PTR1(<4 x i8>* %p) nounwind {
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entry:
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%G = load <4 x i8>* %p
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;CHECK: movl
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;CHECK: pmovzxbd (%
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%K = inttoptr <4 x i8> %G to <4 x i32*>
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;CHECK: ret
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ret <4 x i32*> %K
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}
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;CHECK: BITCAST0
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define <4 x i32*> @BITCAST0(<4 x i8*>* %p) nounwind {
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entry:
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%G = load <4 x i8*>* %p
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;CHECK: movl
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%T = bitcast <4 x i8*> %G to <4 x i32*>
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;CHECK: movaps
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;CHECK: ret
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ret <4 x i32*> %T
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}
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;CHECK: BITCAST1
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define <2 x i32*> @BITCAST1(<2 x i8*>* %p) nounwind {
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entry:
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%G = load <2 x i8*>* %p
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;CHECK: movl
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;CHECK: pmovzxdq
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%T = bitcast <2 x i8*> %G to <2 x i32*>
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;CHECK: ret
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ret <2 x i32*> %T
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}
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;CHECK: ICMP0
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define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
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entry:
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%g0 = load <4 x i8*>* %p0
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%g1 = load <4 x i8*>* %p1
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%k = icmp sgt <4 x i8*> %g0, %g1
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;CHECK: pcmpgtd
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%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
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ret <4 x i32> %j
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;CHECK: ret
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}
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;CHECK: ICMP1
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define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
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entry:
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%g0 = load <4 x i8*>* %p0
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%g1 = load <4 x i8*>* %p1
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%k = icmp eq <4 x i8*> %g0, %g1
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;CHECK: pcmpeqd
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%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
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ret <4 x i32> %j
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;CHECK: ret
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}
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