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https://github.com/c64scene-ar/llvm-6502.git
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04715c9915
Implement a BITCAST dag combine to transform i32->mmx conversion patterns into a X86 specific node (MMX_MOVW2D) and guarantee that moves between i32 and x86mmx are better handled, i.e., don't use store-load to do the conversion.. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228293 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.3 KiB
LLVM
72 lines
2.3 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-darwin -x86-experimental-vector-widening-legalization -mattr=+mmx,+sse2 | FileCheck %s
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define i32 @test0(<1 x i64>* %v4) {
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; CHECK-LABEL: test0:
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; CHECK: ## BB#0:
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; CHECK-NEXT: pshufw $238, (%rdi), %mm0
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; CHECK-NEXT: movd %mm0, %eax
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; CHECK-NEXT: addl $32, %eax
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; CHECK-NEXT: retq
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%v5 = load <1 x i64>* %v4, align 8
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%v12 = bitcast <1 x i64> %v5 to <4 x i16>
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%v13 = bitcast <4 x i16> %v12 to x86_mmx
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%v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
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%v15 = bitcast x86_mmx %v14 to <4 x i16>
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%v16 = bitcast <4 x i16> %v15 to <1 x i64>
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%v17 = extractelement <1 x i64> %v16, i32 0
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%v18 = bitcast i64 %v17 to <2 x i32>
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%v19 = extractelement <2 x i32> %v18, i32 0
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%v20 = add i32 %v19, 32
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ret i32 %v20
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}
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define i32 @test1(i32* nocapture readonly %ptr) {
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; CHECK-LABEL: test1:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: movd (%rdi), %mm0
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; CHECK-NEXT: pshufw $232, %mm0, %mm0
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; CHECK-NEXT: movd %mm0, %eax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%0 = load i32* %ptr, align 4
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%1 = insertelement <2 x i32> undef, i32 %0, i32 0
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%2 = insertelement <2 x i32> %1, i32 0, i32 1
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%3 = bitcast <2 x i32> %2 to x86_mmx
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%4 = bitcast x86_mmx %3 to i64
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%5 = bitcast i64 %4 to <4 x i16>
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%6 = bitcast <4 x i16> %5 to x86_mmx
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%7 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %6, i8 -24)
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%8 = bitcast x86_mmx %7 to <4 x i16>
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%9 = bitcast <4 x i16> %8 to <1 x i64>
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%10 = extractelement <1 x i64> %9, i32 0
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%11 = bitcast i64 %10 to <2 x i32>
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%12 = extractelement <2 x i32> %11, i32 0
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tail call void @llvm.x86.mmx.emms()
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ret i32 %12
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}
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define i32 @test2(i32* nocapture readonly %ptr) {
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; CHECK-LABEL: test2:
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; CHECK: ## BB#0: ## %entry
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: pshufw $232, %mm0, %mm0
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; CHECK-NEXT: movd %mm0, %eax
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast i32* %ptr to x86_mmx*
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%1 = load x86_mmx* %0, align 8
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%2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
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%3 = bitcast x86_mmx %2 to <4 x i16>
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%4 = bitcast <4 x i16> %3 to <1 x i64>
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%5 = extractelement <1 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <2 x i32>
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%7 = extractelement <2 x i32> %6, i32 0
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tail call void @llvm.x86.mmx.emms()
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ret i32 %7
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}
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declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
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declare void @llvm.x86.mmx.emms()
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