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11a1dfffc8b6bbe0c0936c2c70681bc74bb5cd56
llvm-6502/test/CodeGen
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Bob Wilson 11a1dfffc8 Lower some BUILD_VECTORS using VEXT+shuffle.
Patch by Tim Northover.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123035 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07 21:37:30 +00:00
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Alpha
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ARM
Lower some BUILD_VECTORS using VEXT+shuffle.
2011-01-07 21:37:30 +00:00
Blackfin
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CBackend
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CellSPU
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CPP
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Generic
Add a testcase for PR8582, which mysteriously fixed itself, in case the problem
2011-01-06 23:04:29 +00:00
MBlaze
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Mips
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MSP430
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PowerPC
Restore the behavior of frame lowering before my refactoring.
2010-12-18 19:53:14 +00:00
PTX
ptx: remove reg-reg addressing mode and st.const
2011-01-01 11:58:58 +00:00
SPARC
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SystemZ
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Thumb
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Thumb2
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
2011-01-07 04:59:04 +00:00
X86
Appropriately truncate debug info range in dwarf output.
2011-01-07 21:30:41 +00:00
XCore
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thumb2-mul.ll
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