Ulrich Weigand 1307d8300f [PowerPC] Support all condition register logical instructions ... This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-01 21:40:54 +00:00
..
Analysis	ValueTracking: Teach isKnownToBeAPowerOfTwo about (ADD X, (XOR X, Y)) where X is a power of two	2013-06-29 23:44:53 +00:00
AsmParser	Added support for the Builtin attribute.	2013-06-27 00:25:01 +00:00
Bitcode
CodeGen	Make PBQP require/preserve MachineLoopInfo - the spiller requires it.	2013-07-01 20:47:47 +00:00
DebugInfo
ExecutionEngine	AArch64: correct CodeGen of MOVZ/MOVK combinations.	2013-07-01 19:23:10 +00:00
IR	Debug Info: clean up usage of Verify.	2013-07-01 21:02:01 +00:00
IRReader
Linker
MC	Use MCFillFragment for zero-initialized data.	2013-06-27 14:35:03 +00:00
Object	Make a switch in createBinary fully-covered. Add forgotten macho_dsym_companion case.	2013-06-28 09:44:05 +00:00
Option	Fix a crash bug in dumping options with groups	2013-06-26 22:43:37 +00:00
Support	Fix a bad overflow check pointed out by Ben.	2013-06-28 21:51:18 +00:00
TableGen
Target	[PowerPC] Support all condition register logical instructions	2013-07-01 21:40:54 +00:00
Transforms	Debug Info: clean up usage of Verify.	2013-07-01 21:02:01 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile