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llvm-6502/lib/Target
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Chris Lattner 138d322e96 fix a bug in my previous checkin 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25244 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-12 07:38:04 +00:00
..
Alpha
Add bswap, rotl, and rotr nodes
2006-01-11 21:21:00 +00:00
CBackend
yet more C++ standards-compliance stuff.
2005-12-27 10:40:34 +00:00
IA64
sabre's (correct) fix means these guys need to be flagged as well (else
2006-01-12 03:28:40 +00:00
PowerPC
ahem :)
2006-01-12 02:05:36 +00:00
Skeleton
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
2005-12-01 04:51:06 +00:00
Sparc
fix a bug in my previous checkin
2006-01-12 07:38:04 +00:00
SparcV8
fix a bug in my previous checkin
2006-01-12 07:38:04 +00:00
SparcV9
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
2005-12-01 04:51:06 +00:00
X86
Added ROTL and ROTR.
2006-01-11 23:20:05 +00:00
Makefile
DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now
2005-10-24 02:26:13 +00:00
MRegisterInfo.cpp
…
SubtargetFeature.cpp
Preparation of supporting scheduling info. Need to find info based on selected
2005-10-25 15:15:28 +00:00
Target.td
New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace
2006-01-09 18:28:21 +00:00
TargetData.cpp
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TargetFrameInfo.cpp
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TargetInstrInfo.cpp
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TargetMachine.cpp
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TargetMachineRegistry.cpp
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TargetSchedInfo.cpp
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TargetSchedule.td
add a marker
2005-10-23 22:07:20 +00:00
TargetSelectionDAG.td
Add bswap, rotl, and rotr nodes
2006-01-11 21:21:00 +00:00
TargetSubtarget.cpp
…