mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-17 06:33:21 +00:00
13a949071c
1. A delay slot filler that searches for valid instructions
to fill the delay slot with. Previously NOPs would always
be inserted into delay slots.
2. Support for MC based instruction printer added.
3. Support for MC based machine code generation and ELF
file generation. ELF file generation does not yet
completely work as much of the ELF support infrastructure
is still x86/x86-64 specific.
4. General clean up of the MBlaze backend code. Much of the
tablegen code has been cleanup and simplified.
Bug Fixes:
1. Removed duplicate periods from subtarget feature descriptions.
2. Many of the instructions had bad machine code information
in the tablegen files. Much of this has been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116986 91177308-0d34-0410-b5e6-96231b3b80d8
670 lines
28 KiB
TableGen
670 lines
28 KiB
TableGen
//===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "MBlazeInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// MBlaze type profiles
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//===----------------------------------------------------------------------===//
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// def SDTMBlazeSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>;
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def SDT_MBlazeRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MBlazeJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def SDT_MBCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MBCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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//===----------------------------------------------------------------------===//
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// MBlaze specific nodes
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//===----------------------------------------------------------------------===//
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def MBlazeRet : SDNode<"MBlazeISD::Ret", SDT_MBlazeRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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def MBlazeJmpLink : SDNode<"MBlazeISD::JmpLink",SDT_MBlazeJmpLink,
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[SDNPHasChain,SDNPOptInFlag,SDNPOutFlag]>;
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def MBWrapper : SDNode<"MBlazeISD::Wrap", SDTIntUnaryOp>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MBCallSeqStart,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MBCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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//===----------------------------------------------------------------------===//
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// MBlaze Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasPipe3 : Predicate<"Subtarget.hasPipe3()">;
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def HasBarrel : Predicate<"Subtarget.hasBarrel()">;
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def NoBarrel : Predicate<"!Subtarget.hasBarrel()">;
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def HasDiv : Predicate<"Subtarget.hasDiv()">;
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def HasMul : Predicate<"Subtarget.hasMul()">;
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def HasFSL : Predicate<"Subtarget.hasFSL()">;
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def HasEFSL : Predicate<"Subtarget.hasEFSL()">;
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def HasMSRSet : Predicate<"Subtarget.hasMSRSet()">;
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def HasException : Predicate<"Subtarget.hasException()">;
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def HasPatCmp : Predicate<"Subtarget.hasPatCmp()">;
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def HasFPU : Predicate<"Subtarget.hasFPU()">;
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def HasESR : Predicate<"Subtarget.hasESR()">;
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def HasPVR : Predicate<"Subtarget.hasPVR()">;
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def HasMul64 : Predicate<"Subtarget.hasMul64()">;
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def HasSqrt : Predicate<"Subtarget.hasSqrt()">;
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def HasMMU : Predicate<"Subtarget.hasMMU()">;
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//===----------------------------------------------------------------------===//
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// MBlaze Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def simm16 : Operand<i32>;
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def uimm5 : Operand<i32>;
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def fimm : Operand<f32>;
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// Unsigned Operand
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def uimm16 : Operand<i32> {
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let PrintMethod = "printUnsignedImm";
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}
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// FSL Operand
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def fslimm : Operand<i32> {
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let PrintMethod = "printFSLImm";
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}
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// Address operand
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def memri : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops simm16, CPURegs);
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}
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def memrr : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPURegs, CPURegs);
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}
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// Node immediate fits as 16-bit sign extended on target immediate.
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def immSExt16 : PatLeaf<(imm), [{
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return (N->getZExtValue() >> 16) == 0;
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}]>;
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// Node immediate fits as 16-bit zero extended on target immediate.
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// The LO16 param means that only the lower 16 bits of the node
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// immediate are caught.
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// e.g. addiu, sltiu
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def immZExt16 : PatLeaf<(imm), [{
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return (N->getZExtValue() >> 16) == 0;
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}]>;
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// FSL immediate field must fit in 4 bits.
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def immZExt4 : PatLeaf<(imm), [{
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return N->getZExtValue() == ((N->getZExtValue()) & 0xf) ;
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}]>;
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// shamt field must fit in 5 bits.
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def immZExt5 : PatLeaf<(imm), [{
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return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
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}]>;
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// MBlaze Address Mode. SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def iaddr : ComplexPattern<i32, 2, "SelectAddrRegImm", [frameindex], []>;
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def xaddr : ComplexPattern<i32, 2, "SelectAddrRegReg", [], []>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [R1], Uses = [R1] in {
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def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt),
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"#ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : MBlazePseudo<(outs),
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(ins uimm16:$amt1, simm16:$amt2),
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"#ADJCALLSTACKUP $amt1",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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class Arith<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
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InstrItinClass itin> :
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TA<op, flags, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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TB<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
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InstrItinClass itin> :
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TA<op, flags, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
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!strconcat(instr_asm, " $dst, $c, $b"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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class ArithRI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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TBR<op, (outs CPURegs:$dst), (ins Od:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $c, $b"),
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[(set CPURegs:$dst, (OpNode imm_type:$b, CPURegs:$c))], IIAlu>;
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class ArithN<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TA<op, flags, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], itin>;
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class ArithNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
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TB<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], IIAlu>;
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class ArithRN<bits<6> op, bits<11> flags, string instr_asm,
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InstrItinClass itin> :
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TA<op, flags, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], itin>;
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class ArithRNI<bits<6> op, string instr_asm,Operand Od, PatLeaf imm_type> :
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TB<op, (outs CPURegs:$dst), (ins Od:$c, CPURegs:$b),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[], IIAlu>;
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//===----------------------------------------------------------------------===//
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// Misc Arithmetic Instructions
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//===----------------------------------------------------------------------===//
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class Logic<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode> :
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TA<op, flags, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode> :
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TB<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
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!strconcat(instr_asm, " $dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))],
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IIAlu>;
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//===----------------------------------------------------------------------===//
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// Memory Access Instructions
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//===----------------------------------------------------------------------===//
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode> :
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TA<op, 0x000, (outs CPURegs:$dst), (ins memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set CPURegs:$dst, (OpNode xaddr:$addr))], IILoad>;
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class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TBR<op, (outs CPURegs:$dst), (ins memri:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set CPURegs:$dst, (OpNode iaddr:$addr))], IILoad>;
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode> :
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TA<op, 0x000, (outs), (ins CPURegs:$dst, memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(OpNode CPURegs:$dst, xaddr:$addr)], IIStore>;
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class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TBR<op, (outs), (ins CPURegs:$dst, memri:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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[(OpNode CPURegs:$dst, iaddr:$addr)], IIStore>;
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//===----------------------------------------------------------------------===//
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// Branch Instructions
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//===----------------------------------------------------------------------===//
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class Branch<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
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TA<op, flags, (outs), (ins CPURegs:$target),
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!strconcat(instr_asm, " $target"),
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[], IIBranch> {
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let rd = 0x0;
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let ra = br;
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}
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class BranchI<bits<6> op, bits<5> br, string instr_asm> :
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TB<op, (outs), (ins brtarget:$target),
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!strconcat(instr_asm, " $target"),
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[], IIBranch> {
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let rd = 0;
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let ra = br;
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}
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//===----------------------------------------------------------------------===//
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// Branch and Link Instructions
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//===----------------------------------------------------------------------===//
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class BranchL<bits<6> op, bits<5> br, bits<11> flags, string instr_asm> :
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TA<op, flags, (outs), (ins CPURegs:$target),
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!strconcat(instr_asm, " r15, $target"),
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[], IIBranch> {
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let rd = 15;
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let ra = br;
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}
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class BranchLI<bits<6> op, bits<5> br, string instr_asm> :
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TB<op, (outs), (ins calltarget:$target),
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!strconcat(instr_asm, " r15, $target"),
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[], IIBranch> {
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let rd = 15;
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let ra = br;
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}
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//===----------------------------------------------------------------------===//
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// Conditional Branch Instructions
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//===----------------------------------------------------------------------===//
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class BranchC<bits<6> op, bits<5> br, bits<11> flags, string instr_asm,
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PatFrag cond_op> :
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TA<op, flags, (outs),
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(ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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!strconcat(instr_asm, " $a, $b, $offset"),
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[], IIBranch> {
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let rd = br;
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}
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class BranchCI<bits<6> op, bits<5> br, string instr_asm, PatFrag cond_op> :
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TB<op, (outs), (ins CPURegs:$a, brtarget:$offset),
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!strconcat(instr_asm, " $a, $offset"),
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[], IIBranch> {
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let rd = br;
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}
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//===----------------------------------------------------------------------===//
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// MBlaze arithmetic instructions
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//===----------------------------------------------------------------------===//
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let isCommutable = 1, isAsCheapAsAMove = 1 in {
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def ADD : Arith<0x00, 0x000, "add ", add, IIAlu>;
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def ADDC : Arith<0x02, 0x000, "addc ", adde, IIAlu>;
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def ADDK : Arith<0x04, 0x000, "addk ", addc, IIAlu>;
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def ADDKC : ArithN<0x06, 0x000, "addkc ", IIAlu>;
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def AND : Logic<0x21, 0x000, "and ", and>;
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def OR : Logic<0x20, 0x000, "or ", or>;
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def XOR : Logic<0x22, 0x000, "xor ", xor>;
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}
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let isAsCheapAsAMove = 1 in {
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def ANDN : ArithN<0x23, 0x000, "andn ", IIAlu>;
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def CMP : ArithN<0x05, 0x001, "cmp ", IIAlu>;
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def CMPU : ArithN<0x05, 0x003, "cmpu ", IIAlu>;
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def RSUB : ArithR<0x01, 0x000, "rsub ", sub, IIAlu>;
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def RSUBC : ArithR<0x03, 0x000, "rsubc ", sube, IIAlu>;
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def RSUBK : ArithR<0x05, 0x000, "rsubk ", subc, IIAlu>;
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def RSUBKC : ArithRN<0x07, 0x000, "rsubkc ", IIAlu>;
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}
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let isCommutable = 1, Predicates=[HasMul] in {
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def MUL : Arith<0x10, 0x000, "mul ", mul, IIAlu>;
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}
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let isCommutable = 1, Predicates=[HasMul,HasMul64] in {
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def MULH : Arith<0x10, 0x001, "mulh ", mulhs, IIAlu>;
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def MULHU : Arith<0x10, 0x003, "mulhu ", mulhu, IIAlu>;
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}
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let Predicates=[HasMul,HasMul64] in {
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def MULHSU : ArithN<0x10, 0x002, "mulhsu ", IIAlu>;
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}
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let Predicates=[HasBarrel] in {
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def BSRL : Arith<0x11, 0x000, "bsrl ", srl, IIAlu>;
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def BSRA : Arith<0x11, 0x200, "bsra ", sra, IIAlu>;
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def BSLL : Arith<0x11, 0x400, "bsll ", shl, IIAlu>;
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def BSRLI : ArithI<0x11, "bsrli ", srl, uimm5, immZExt5>;
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def BSRAI : ArithI<0x11, "bsrai ", sra, uimm5, immZExt5>;
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def BSLLI : ArithI<0x11, "bslli ", shl, uimm5, immZExt5>;
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}
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let Predicates=[HasDiv] in {
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def IDIV : Arith<0x12, 0x000, "idiv ", sdiv, IIAlu>;
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def IDIVU : Arith<0x12, 0x002, "idivu ", udiv, IIAlu>;
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}
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//===----------------------------------------------------------------------===//
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// MBlaze immediate mode arithmetic instructions
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//===----------------------------------------------------------------------===//
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let isAsCheapAsAMove = 1 in {
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def ADDI : ArithI<0x08, "addi ", add, simm16, immSExt16>;
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def ADDIC : ArithNI<0x0A, "addic ", simm16, immSExt16>;
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def ADDIK : ArithNI<0x0C, "addik ", simm16, immSExt16>;
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def ADDIKC : ArithI<0x0E, "addikc ", addc, simm16, immSExt16>;
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def RSUBI : ArithRI<0x09, "rsubi ", sub, simm16, immSExt16>;
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def RSUBIC : ArithRNI<0x0B, "rsubi ", simm16, immSExt16>;
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def RSUBIK : ArithRNI<0x0E, "rsubic ", simm16, immSExt16>;
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def RSUBIKC : ArithRI<0x0F, "rsubikc", subc, simm16, immSExt16>;
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def ANDNI : ArithNI<0x2B, "andni ", uimm16, immZExt16>;
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def ANDI : LogicI<0x29, "andi ", and>;
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def ORI : LogicI<0x28, "ori ", or>;
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def XORI : LogicI<0x2A, "xori ", xor>;
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}
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let Predicates=[HasMul] in {
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def MULI : ArithI<0x18, "muli ", mul, simm16, immSExt16>;
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}
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//===----------------------------------------------------------------------===//
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// MBlaze memory access instructions
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//===----------------------------------------------------------------------===//
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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def LBU : LoadM<0x30, "lbu ", zextloadi8>;
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def LHU : LoadM<0x31, "lhu ", zextloadi16>;
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def LW : LoadM<0x32, "lw ", load>;
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def LBUI : LoadMI<0x38, "lbui ", zextloadi8>;
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def LHUI : LoadMI<0x39, "lhui ", zextloadi16>;
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def LWI : LoadMI<0x3A, "lwi ", load>;
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}
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def SB : StoreM<0x34, "sb ", truncstorei8>;
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def SH : StoreM<0x35, "sh ", truncstorei16>;
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def SW : StoreM<0x36, "sw ", store>;
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def SBI : StoreMI<0x3C, "sbi ", truncstorei8>;
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def SHI : StoreMI<0x3D, "shi ", truncstorei16>;
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def SWI : StoreMI<0x3E, "swi ", store>;
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//===----------------------------------------------------------------------===//
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// MBlaze branch instructions
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//===----------------------------------------------------------------------===//
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1,
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Form = FI in {
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def BRI : BranchI<0x2E, 0x00, "bri ">;
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def BRAI : BranchI<0x2E, 0x08, "brai ">;
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}
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, Form = FRI in {
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def BEQI : BranchCI<0x2F, 0x00, "beqi ", seteq>;
|
|
def BNEI : BranchCI<0x2F, 0x01, "bnei ", setne>;
|
|
def BLTI : BranchCI<0x2F, 0x02, "blti ", setlt>;
|
|
def BLEI : BranchCI<0x2F, 0x03, "blei ", setle>;
|
|
def BGTI : BranchCI<0x2F, 0x04, "bgti ", setgt>;
|
|
def BGEI : BranchCI<0x2F, 0x05, "bgei ", setge>;
|
|
}
|
|
|
|
let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
|
|
isBarrier = 1, Form = FR in {
|
|
def BR : Branch<0x26, 0x00, 0x000, "br ">;
|
|
def BRA : Branch<0x26, 0x08, 0x000, "bra ">;
|
|
}
|
|
|
|
let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, hasCtrlDep = 1,
|
|
Form = FRR in {
|
|
def BEQ : BranchC<0x27, 0x00, 0x000, "beq ", seteq>;
|
|
def BNE : BranchC<0x27, 0x01, 0x000, "bne ", setne>;
|
|
def BLT : BranchC<0x27, 0x02, 0x000, "blt ", setlt>;
|
|
def BLE : BranchC<0x27, 0x03, 0x000, "ble ", setle>;
|
|
def BGT : BranchC<0x27, 0x04, 0x000, "bgt ", setgt>;
|
|
def BGE : BranchC<0x27, 0x05, 0x000, "bge ", setge>;
|
|
}
|
|
|
|
let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
|
|
isBarrier = 1, Form = FI in {
|
|
def BRID : BranchI<0x2E, 0x10, "brid ">;
|
|
def BRAID : BranchI<0x2E, 0x18, "braid ">;
|
|
}
|
|
|
|
let isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasCtrlDep = 1,
|
|
Form = FRI in {
|
|
def BEQID : BranchCI<0x2F, 0x10, "beqid ", seteq>;
|
|
def BNEID : BranchCI<0x2F, 0x11, "bneid ", setne>;
|
|
def BLTID : BranchCI<0x2F, 0x12, "bltid ", setlt>;
|
|
def BLEID : BranchCI<0x2F, 0x13, "bleid ", setle>;
|
|
def BGTID : BranchCI<0x2F, 0x14, "bgtid ", setgt>;
|
|
def BGEID : BranchCI<0x2F, 0x15, "bgeid ", setge>;
|
|
}
|
|
|
|
let isBranch = 1, isIndirectBranch = 1, isTerminator = 1, Form = FR,
|
|
hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1 in {
|
|
def BRD : Branch<0x26, 0x10, 0x000, "brd ">;
|
|
def BRAD : Branch<0x26, 0x18, 0x000, "brad ">;
|
|
}
|
|
|
|
let isBranch = 1, isIndirectBranch = 1, isTerminator = 1,
|
|
hasDelaySlot = 1, hasCtrlDep = 1, Form = FRR in {
|
|
def BEQD : BranchC<0x27, 0x10, 0x000, "beqd ", seteq>;
|
|
def BNED : BranchC<0x27, 0x11, 0x000, "bned ", setne>;
|
|
def BLTD : BranchC<0x27, 0x12, 0x000, "bltd ", setlt>;
|
|
def BLED : BranchC<0x27, 0x13, 0x000, "bled ", setle>;
|
|
def BGTD : BranchC<0x27, 0x14, 0x000, "bgtd ", setgt>;
|
|
def BGED : BranchC<0x27, 0x15, 0x000, "bged ", setge>;
|
|
}
|
|
|
|
let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isBarrier = 1, Form = FI,
|
|
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
|
|
Uses = [R1,R5,R6,R7,R8,R9,R10] in {
|
|
def BRLID : BranchLI<0x2E, 0x14, "brlid ">;
|
|
def BRALID : BranchLI<0x2E, 0x1C, "bralid ">;
|
|
}
|
|
|
|
let isCall = 1, hasDelaySlot = 1, hasCtrlDep = 1, isIndirectBranch = 1,
|
|
isBarrier = 1, Form = FR,
|
|
Defs = [R3,R4,R5,R6,R7,R8,R9,R10,R11,R12],
|
|
Uses = [R1,R5,R6,R7,R8,R9,R10] in {
|
|
def BRLD : BranchL<0x26, 0x14, 0x000, "brld ">;
|
|
def BRALD : BranchL<0x26, 0x1C, 0x000, "brald ">;
|
|
}
|
|
|
|
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1,
|
|
hasCtrlDep=1, rd=0x10, imm16=0x8, Form=FR in {
|
|
def RTSD : TB<0x2D, (outs), (ins CPURegs:$target),
|
|
"rtsd $target, 8",
|
|
[(MBlazeRet CPURegs:$target)],
|
|
IIBranch>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MBlaze misc instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let neverHasSideEffects = 1 in {
|
|
def NOP : MBlazeInst< 0x20, FRRR, (outs), (ins), "nop ", [], IIAlu>;
|
|
}
|
|
|
|
let usesCustomInserter = 1 in {
|
|
def Select_CC : MBlazePseudo<(outs CPURegs:$dst),
|
|
(ins CPURegs:$T, CPURegs:$F, CPURegs:$CMP, i32imm:$CC),
|
|
"; SELECT_CC PSEUDO!",
|
|
[]>;
|
|
|
|
def ShiftL : MBlazePseudo<(outs CPURegs:$dst),
|
|
(ins CPURegs:$L, CPURegs:$R),
|
|
"; ShiftL PSEUDO!",
|
|
[]>;
|
|
|
|
def ShiftRA : MBlazePseudo<(outs CPURegs:$dst),
|
|
(ins CPURegs:$L, CPURegs:$R),
|
|
"; ShiftRA PSEUDO!",
|
|
[]>;
|
|
|
|
def ShiftRL : MBlazePseudo<(outs CPURegs:$dst),
|
|
(ins CPURegs:$L, CPURegs:$R),
|
|
"; ShiftRL PSEUDO!",
|
|
[]>;
|
|
}
|
|
|
|
|
|
let rb = 0 in {
|
|
def SEXT16 : TA<0x24, 0x061, (outs CPURegs:$dst), (ins CPURegs:$src),
|
|
"sext16 $dst, $src", [], IIAlu>;
|
|
def SEXT8 : TA<0x24, 0x060, (outs CPURegs:$dst), (ins CPURegs:$src),
|
|
"sext8 $dst, $src", [], IIAlu>;
|
|
def SRL : TA<0x24, 0x041, (outs CPURegs:$dst), (ins CPURegs:$src),
|
|
"srl $dst, $src", [], IIAlu>;
|
|
def SRA : TA<0x24, 0x001, (outs CPURegs:$dst), (ins CPURegs:$src),
|
|
"sra $dst, $src", [], IIAlu>;
|
|
def SRC : TA<0x24, 0x021, (outs CPURegs:$dst), (ins CPURegs:$src),
|
|
"src $dst, $src", [], IIAlu>;
|
|
}
|
|
|
|
let opcode=0x08 in {
|
|
def LEA_ADDI : TB<0x08, (outs CPURegs:$dst), (ins memri:$addr),
|
|
"addi $dst, ${addr:stackloc}",
|
|
[(set CPURegs:$dst, iaddr:$addr)], IIAlu>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arbitrary patterns that map to one or more instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Small immediates
|
|
def : Pat<(i32 0), (ADD R0, R0)>;
|
|
def : Pat<(i32 immSExt16:$imm), (ADDI R0, imm:$imm)>;
|
|
def : Pat<(i32 immZExt16:$imm), (ORI R0, imm:$imm)>;
|
|
|
|
// Arbitrary immediates
|
|
def : Pat<(i32 imm:$imm), (ADDI R0, imm:$imm)>;
|
|
|
|
// In register sign extension
|
|
def : Pat<(sext_inreg CPURegs:$src, i16), (SEXT16 CPURegs:$src)>;
|
|
def : Pat<(sext_inreg CPURegs:$src, i8), (SEXT8 CPURegs:$src)>;
|
|
|
|
// Call
|
|
def : Pat<(MBlazeJmpLink (i32 tglobaladdr:$dst)), (BRLID tglobaladdr:$dst)>;
|
|
def : Pat<(MBlazeJmpLink (i32 texternalsym:$dst)),(BRLID texternalsym:$dst)>;
|
|
def : Pat<(MBlazeJmpLink CPURegs:$dst), (BRLD CPURegs:$dst)>;
|
|
|
|
// Shift Instructions
|
|
def : Pat<(shl CPURegs:$L, CPURegs:$R), (ShiftL CPURegs:$L, CPURegs:$R)>;
|
|
def : Pat<(sra CPURegs:$L, CPURegs:$R), (ShiftRA CPURegs:$L, CPURegs:$R)>;
|
|
def : Pat<(srl CPURegs:$L, CPURegs:$R), (ShiftRL CPURegs:$L, CPURegs:$R)>;
|
|
|
|
// SET_CC operations
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETEQ),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMP CPURegs:$L, CPURegs:$R), 1)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETNE),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMP CPURegs:$L, CPURegs:$R), 2)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETGT),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMP CPURegs:$L, CPURegs:$R), 3)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETLT),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMP CPURegs:$L, CPURegs:$R), 4)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETGE),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMP CPURegs:$L, CPURegs:$R), 5)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETLE),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMP CPURegs:$L, CPURegs:$R), 6)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETUGT),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMPU CPURegs:$L, CPURegs:$R), 3)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETULT),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMPU CPURegs:$L, CPURegs:$R), 4)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETUGE),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMPU CPURegs:$L, CPURegs:$R), 5)>;
|
|
def : Pat<(setcc CPURegs:$L, CPURegs:$R, SETULE),
|
|
(Select_CC (ADDI R0, 1), (ADDI R0, 0),
|
|
(CMPU CPURegs:$L, CPURegs:$R), 6)>;
|
|
|
|
// SELECT operations
|
|
def : Pat<(select CPURegs:$C, CPURegs:$T, CPURegs:$F),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, CPURegs:$C, 2)>;
|
|
|
|
// SELECT_CC
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETEQ),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMP CPURegs:$L, CPURegs:$R), 1)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETNE),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMP CPURegs:$L, CPURegs:$R), 2)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETGT),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMP CPURegs:$L, CPURegs:$R), 3)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETLT),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMP CPURegs:$L, CPURegs:$R), 4)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETGE),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMP CPURegs:$L, CPURegs:$R), 5)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETLE),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMP CPURegs:$L, CPURegs:$R), 6)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETUGT),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMPU CPURegs:$L, CPURegs:$R), 3)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETULT),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMPU CPURegs:$L, CPURegs:$R), 4)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETUGE),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMPU CPURegs:$L, CPURegs:$R), 5)>;
|
|
def : Pat<(selectcc CPURegs:$L, CPURegs:$R, CPURegs:$T, CPURegs:$F, SETULE),
|
|
(Select_CC CPURegs:$T, CPURegs:$F, (CMPU CPURegs:$L, CPURegs:$R), 6)>;
|
|
|
|
// BR instructions
|
|
def : Pat<(br bb:$T), (BRID bb:$T)>;
|
|
def : Pat<(brind CPURegs:$T), (BRD CPURegs:$T)>;
|
|
|
|
// BRCOND instructions
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETEQ), bb:$T),
|
|
(BEQID (CMP CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETNE), bb:$T),
|
|
(BNEID (CMP CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETGT), bb:$T),
|
|
(BGTID (CMP CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETLT), bb:$T),
|
|
(BLTID (CMP CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETGE), bb:$T),
|
|
(BGEID (CMP CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETLE), bb:$T),
|
|
(BLEID (CMP CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETUGT), bb:$T),
|
|
(BGTID (CMPU CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETULT), bb:$T),
|
|
(BLTID (CMPU CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETUGE), bb:$T),
|
|
(BGEID (CMPU CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond (setcc CPURegs:$L, CPURegs:$R, SETULE), bb:$T),
|
|
(BLEID (CMPU CPURegs:$R, CPURegs:$L), bb:$T)>;
|
|
def : Pat<(brcond CPURegs:$C, bb:$T),
|
|
(BNEID CPURegs:$C, bb:$T)>;
|
|
|
|
// Jump tables, global addresses, and constant pools
|
|
def : Pat<(MBWrapper tglobaladdr:$in), (ORI R0, tglobaladdr:$in)>;
|
|
def : Pat<(MBWrapper tjumptable:$in), (ORI R0, tjumptable:$in)>;
|
|
def : Pat<(MBWrapper tconstpool:$in), (ORI R0, tconstpool:$in)>;
|
|
|
|
// Misc instructions
|
|
def : Pat<(and CPURegs:$lh, (not CPURegs:$rh)),(ANDN CPURegs:$lh, CPURegs:$rh)>;
|
|
|
|
// Arithmetic with immediates
|
|
def : Pat<(add CPURegs:$in, imm:$imm),(ADDI CPURegs:$in, imm:$imm)>;
|
|
def : Pat<(or CPURegs:$in, imm:$imm),(ORI CPURegs:$in, imm:$imm)>;
|
|
def : Pat<(xor CPURegs:$in, imm:$imm),(XORI CPURegs:$in, imm:$imm)>;
|
|
|
|
// extended load and stores
|
|
def : Pat<(extloadi1 iaddr:$src), (LBUI iaddr:$src)>;
|
|
def : Pat<(extloadi8 iaddr:$src), (LBUI iaddr:$src)>;
|
|
def : Pat<(extloadi16 iaddr:$src), (LHUI iaddr:$src)>;
|
|
def : Pat<(extloadi1 xaddr:$src), (LBU xaddr:$src)>;
|
|
def : Pat<(extloadi8 xaddr:$src), (LBU xaddr:$src)>;
|
|
def : Pat<(extloadi16 xaddr:$src), (LHU xaddr:$src)>;
|
|
|
|
def : Pat<(sextloadi1 iaddr:$src), (SEXT8 (LBUI iaddr:$src))>;
|
|
def : Pat<(sextloadi8 iaddr:$src), (SEXT8 (LBUI iaddr:$src))>;
|
|
def : Pat<(sextloadi16 iaddr:$src), (SEXT16 (LHUI iaddr:$src))>;
|
|
def : Pat<(sextloadi1 xaddr:$src), (SEXT8 (LBU xaddr:$src))>;
|
|
def : Pat<(sextloadi8 xaddr:$src), (SEXT8 (LBU xaddr:$src))>;
|
|
def : Pat<(sextloadi16 xaddr:$src), (SEXT16 (LHU xaddr:$src))>;
|
|
|
|
// peepholes
|
|
def : Pat<(store (i32 0), iaddr:$dst), (SWI R0, iaddr:$dst)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Support
|
|
//===----------------------------------------------------------------------===//
|
|
include "MBlazeInstrFSL.td"
|
|
include "MBlazeInstrFPU.td"
|