llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-08 03:30:22 +00:00

History

Rafael Espindola 9e071f0ae3 fix the names of the 64bit fp register initial support for returning 64bit floating point numbers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8		2006-10-02 19:30:56 +00:00
..
.cvsignore
ARM.h	Implement a MachineFunctionPass to fix the mul instruction	2006-09-19 15:49:25 +00:00
ARM.td
ARMAsmPrinter.cpp
ARMFrameInfo.h
ARMInstrInfo.cpp
ARMInstrInfo.h
ARMInstrInfo.td	fix the names of the 64bit fp register	2006-10-02 19:30:56 +00:00
ARMISelDAGToDAG.cpp	fix the names of the 64bit fp register	2006-10-02 19:30:56 +00:00
ARMMul.cpp	fix header	2006-09-19 16:41:40 +00:00
ARMRegisterInfo.cpp
ARMRegisterInfo.h
ARMRegisterInfo.td	fix the names of the 64bit fp register	2006-10-02 19:30:56 +00:00
ARMTargetAsmInfo.cpp
ARMTargetAsmInfo.h
ARMTargetMachine.cpp	Implement a MachineFunctionPass to fix the mul instruction	2006-09-19 15:49:25 +00:00
ARMTargetMachine.h	Implement a MachineFunctionPass to fix the mul instruction	2006-09-19 15:49:25 +00:00
Makefile
README.txt	add a note	2006-09-22 11:36:17 +00:00

README.txt

//===---------------------------------------------------------------------===//
// Random ideas for the ARM backend.
//===---------------------------------------------------------------------===//

Consider implementing a select with two conditional moves:

cmp x, y
moveq dst, a
movne dst, b

----------------------------------------------------------


%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %a, %tmp1

compiles to

add r0, r0, r1, lsl r2

but

%tmp1 = shl int %b, ubyte %c
%tmp4 = add int %tmp1, %a

compiles to
mov r1, r1, lsl r2
add r0, r1, r0

----------------------------------------------------------