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https://github.com/c64scene-ar/llvm-6502.git
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c7f3ace20c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
1822 lines
69 KiB
C++
1822 lines
69 KiB
C++
//===-- ARMConstantIslandPass.cpp - ARM constant islands --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that splits the constant pool up into 'islands'
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// which are scattered through-out the function. This is required due to the
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// limited pc-relative displacements that ARM has.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-cp-islands"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMInstrInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumCPEs, "Number of constpool entries");
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STATISTIC(NumSplit, "Number of uncond branches inserted");
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STATISTIC(NumCBrFixed, "Number of cond branches fixed");
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STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
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STATISTIC(NumTBs, "Number of table branches generated");
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STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
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STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
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STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
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STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
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STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
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static cl::opt<bool>
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AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
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cl::desc("Adjust basic block layout to better use TB[BH]"));
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namespace {
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/// ARMConstantIslands - Due to limited PC-relative displacements, ARM
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/// requires constant pool entries to be scattered among the instructions
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/// inside a function. To do this, it completely ignores the normal LLVM
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/// constant pool; instead, it places constants wherever it feels like with
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/// special instructions.
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///
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/// The terminology used in this pass includes:
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/// Islands - Clumps of constants placed in the function.
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/// Water - Potential places where an island could be formed.
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/// CPE - A constant pool entry that has been placed somewhere, which
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/// tracks a list of users.
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class ARMConstantIslands : public MachineFunctionPass {
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/// BBSizes - The size of each MachineBasicBlock in bytes of code, indexed
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/// by MBB Number. The two-byte pads required for Thumb alignment are
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/// counted as part of the following block (i.e., the offset and size for
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/// a padded block will both be ==2 mod 4).
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std::vector<unsigned> BBSizes;
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/// BBOffsets - the offset of each MBB in bytes, starting from 0.
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/// The two-byte pads required for Thumb alignment are counted as part of
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/// the following block.
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std::vector<unsigned> BBOffsets;
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/// WaterList - A sorted list of basic blocks where islands could be placed
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/// (i.e. blocks that don't fall through to the following block, due
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/// to a return, unreachable, or unconditional branch).
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std::vector<MachineBasicBlock*> WaterList;
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/// NewWaterList - The subset of WaterList that was created since the
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/// previous iteration by inserting unconditional branches.
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SmallSet<MachineBasicBlock*, 4> NewWaterList;
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typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
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/// CPUser - One user of a constant pool, keeping the machine instruction
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/// pointer, the constant pool being referenced, and the max displacement
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/// allowed from the instruction to the CP. The HighWaterMark records the
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/// highest basic block where a new CPEntry can be placed. To ensure this
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/// pass terminates, the CP entries are initially placed at the end of the
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/// function and then move monotonically to lower addresses. The
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/// exception to this rule is when the current CP entry for a particular
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/// CPUser is out of range, but there is another CP entry for the same
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/// constant value in range. We want to use the existing in-range CP
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/// entry, but if it later moves out of range, the search for new water
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/// should resume where it left off. The HighWaterMark is used to record
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/// that point.
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struct CPUser {
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MachineInstr *MI;
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MachineInstr *CPEMI;
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MachineBasicBlock *HighWaterMark;
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unsigned MaxDisp;
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bool NegOk;
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bool IsSoImm;
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CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
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bool neg, bool soimm)
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: MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {
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HighWaterMark = CPEMI->getParent();
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}
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};
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/// CPUsers - Keep track of all of the machine instructions that use various
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/// constant pools and their max displacement.
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std::vector<CPUser> CPUsers;
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/// CPEntry - One per constant pool entry, keeping the machine instruction
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/// pointer, the constpool index, and the number of CPUser's which
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/// reference this entry.
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struct CPEntry {
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MachineInstr *CPEMI;
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unsigned CPI;
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unsigned RefCount;
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CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
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: CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
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};
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/// CPEntries - Keep track of all of the constant pool entry machine
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/// instructions. For each original constpool index (i.e. those that
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/// existed upon entry to this pass), it keeps a vector of entries.
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/// Original elements are cloned as we go along; the clones are
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/// put in the vector of the original element, but have distinct CPIs.
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std::vector<std::vector<CPEntry> > CPEntries;
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/// ImmBranch - One per immediate branch, keeping the machine instruction
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/// pointer, conditional or unconditional, the max displacement,
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/// and (if isCond is true) the corresponding unconditional branch
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/// opcode.
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struct ImmBranch {
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MachineInstr *MI;
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unsigned MaxDisp : 31;
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bool isCond : 1;
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int UncondBr;
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ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, int ubr)
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: MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
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};
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/// ImmBranches - Keep track of all the immediate branch instructions.
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///
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std::vector<ImmBranch> ImmBranches;
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/// PushPopMIs - Keep track of all the Thumb push / pop instructions.
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///
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SmallVector<MachineInstr*, 4> PushPopMIs;
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/// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
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SmallVector<MachineInstr*, 4> T2JumpTables;
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/// HasFarJump - True if any far jump instruction has been emitted during
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/// the branch fix up pass.
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bool HasFarJump;
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/// HasInlineAsm - True if the function contains inline assembly.
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bool HasInlineAsm;
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const TargetInstrInfo *TII;
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const ARMSubtarget *STI;
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ARMFunctionInfo *AFI;
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bool isThumb;
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bool isThumb1;
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bool isThumb2;
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public:
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static char ID;
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ARMConstantIslands() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "ARM constant island placement and branch shortening pass";
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}
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private:
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void DoInitialPlacement(MachineFunction &MF,
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std::vector<MachineInstr*> &CPEMIs);
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CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
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void JumpTableFunctionScan(MachineFunction &MF);
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void InitialFunctionScan(MachineFunction &MF,
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const std::vector<MachineInstr*> &CPEMIs);
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MachineBasicBlock *SplitBlockBeforeInstr(MachineInstr *MI);
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void UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB);
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void AdjustBBOffsetsAfter(MachineBasicBlock *BB, int delta);
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bool DecrementOldEntry(unsigned CPI, MachineInstr* CPEMI);
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int LookForExistingCPEntry(CPUser& U, unsigned UserOffset);
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bool LookForWater(CPUser&U, unsigned UserOffset, water_iterator &WaterIter);
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void CreateNewWater(unsigned CPUserIndex, unsigned UserOffset,
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MachineBasicBlock *&NewMBB);
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bool HandleConstantPoolUser(MachineFunction &MF, unsigned CPUserIndex);
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void RemoveDeadCPEMI(MachineInstr *CPEMI);
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bool RemoveUnusedCPEntries();
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bool CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
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MachineInstr *CPEMI, unsigned Disp, bool NegOk,
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bool DoDump = false);
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bool WaterIsInRange(unsigned UserOffset, MachineBasicBlock *Water,
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CPUser &U);
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bool OffsetIsInRange(unsigned UserOffset, unsigned TrialOffset,
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unsigned Disp, bool NegativeOK, bool IsSoImm = false);
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bool BBIsInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
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bool FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br);
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bool FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br);
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bool FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br);
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bool UndoLRSpillRestore();
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bool OptimizeThumb2Instructions(MachineFunction &MF);
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bool OptimizeThumb2Branches(MachineFunction &MF);
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bool ReorderThumb2JumpTables(MachineFunction &MF);
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bool OptimizeThumb2JumpTables(MachineFunction &MF);
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MachineBasicBlock *AdjustJTTargetBlockForward(MachineBasicBlock *BB,
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MachineBasicBlock *JTBB);
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unsigned GetOffsetOf(MachineInstr *MI) const;
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void dumpBBs();
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void verify(MachineFunction &MF);
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};
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char ARMConstantIslands::ID = 0;
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}
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/// verify - check BBOffsets, BBSizes, alignment of islands
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void ARMConstantIslands::verify(MachineFunction &MF) {
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assert(BBOffsets.size() == BBSizes.size());
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for (unsigned i = 1, e = BBOffsets.size(); i != e; ++i)
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assert(BBOffsets[i-1]+BBSizes[i-1] == BBOffsets[i]);
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if (!isThumb)
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return;
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#ifndef NDEBUG
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for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
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MBBI != E; ++MBBI) {
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MachineBasicBlock *MBB = MBBI;
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if (!MBB->empty() &&
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MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
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unsigned MBBId = MBB->getNumber();
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assert(HasInlineAsm ||
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(BBOffsets[MBBId]%4 == 0 && BBSizes[MBBId]%4 == 0) ||
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(BBOffsets[MBBId]%4 != 0 && BBSizes[MBBId]%4 != 0));
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}
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}
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for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
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CPUser &U = CPUsers[i];
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unsigned UserOffset = GetOffsetOf(U.MI) + (isThumb ? 4 : 8);
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unsigned CPEOffset = GetOffsetOf(U.CPEMI);
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unsigned Disp = UserOffset < CPEOffset ? CPEOffset - UserOffset :
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UserOffset - CPEOffset;
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assert(Disp <= U.MaxDisp || "Constant pool entry out of range!");
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}
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#endif
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}
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/// print block size and offset information - debugging
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void ARMConstantIslands::dumpBBs() {
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for (unsigned J = 0, E = BBOffsets.size(); J !=E; ++J) {
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DEBUG(errs() << "block " << J << " offset " << BBOffsets[J]
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<< " size " << BBSizes[J] << "\n");
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}
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}
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/// createARMConstantIslandPass - returns an instance of the constpool
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/// island pass.
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FunctionPass *llvm::createARMConstantIslandPass() {
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return new ARMConstantIslands();
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}
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bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
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MachineConstantPool &MCP = *MF.getConstantPool();
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TII = MF.getTarget().getInstrInfo();
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AFI = MF.getInfo<ARMFunctionInfo>();
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STI = &MF.getTarget().getSubtarget<ARMSubtarget>();
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isThumb = AFI->isThumbFunction();
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isThumb1 = AFI->isThumb1OnlyFunction();
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isThumb2 = AFI->isThumb2Function();
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HasFarJump = false;
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HasInlineAsm = false;
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// Renumber all of the machine basic blocks in the function, guaranteeing that
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// the numbers agree with the position of the block in the function.
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MF.RenumberBlocks();
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// Try to reorder and otherwise adjust the block layout to make good use
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// of the TB[BH] instructions.
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bool MadeChange = false;
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if (isThumb2 && AdjustJumpTableBlocks) {
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JumpTableFunctionScan(MF);
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MadeChange |= ReorderThumb2JumpTables(MF);
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// Data is out of date, so clear it. It'll be re-computed later.
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T2JumpTables.clear();
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// Blocks may have shifted around. Keep the numbering up to date.
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MF.RenumberBlocks();
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}
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// Thumb1 functions containing constant pools get 4-byte alignment.
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// This is so we can keep exact track of where the alignment padding goes.
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// ARM and Thumb2 functions need to be 4-byte aligned.
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if (!isThumb1)
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MF.EnsureAlignment(2); // 2 = log2(4)
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// Perform the initial placement of the constant pool entries. To start with,
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// we put them all at the end of the function.
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std::vector<MachineInstr*> CPEMIs;
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if (!MCP.isEmpty()) {
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DoInitialPlacement(MF, CPEMIs);
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if (isThumb1)
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MF.EnsureAlignment(2); // 2 = log2(4)
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}
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/// The next UID to take is the first unused one.
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AFI->initConstPoolEntryUId(CPEMIs.size());
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// Do the initial scan of the function, building up information about the
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// sizes of each block, the location of all the water, and finding all of the
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// constant pool users.
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InitialFunctionScan(MF, CPEMIs);
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CPEMIs.clear();
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/// Remove dead constant pool entries.
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RemoveUnusedCPEntries();
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// Iteratively place constant pool entries and fix up branches until there
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// is no change.
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unsigned NoCPIters = 0, NoBRIters = 0;
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while (true) {
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bool CPChange = false;
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for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
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CPChange |= HandleConstantPoolUser(MF, i);
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if (CPChange && ++NoCPIters > 30)
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llvm_unreachable("Constant Island pass failed to converge!");
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DEBUG(dumpBBs());
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// Clear NewWaterList now. If we split a block for branches, it should
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// appear as "new water" for the next iteration of constant pool placement.
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NewWaterList.clear();
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bool BRChange = false;
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for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
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BRChange |= FixUpImmediateBr(MF, ImmBranches[i]);
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if (BRChange && ++NoBRIters > 30)
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llvm_unreachable("Branch Fix Up pass failed to converge!");
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DEBUG(dumpBBs());
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if (!CPChange && !BRChange)
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break;
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MadeChange = true;
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}
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// Shrink 32-bit Thumb2 branch, load, and store instructions.
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if (isThumb2)
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MadeChange |= OptimizeThumb2Instructions(MF);
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// After a while, this might be made debug-only, but it is not expensive.
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verify(MF);
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// If LR has been forced spilled and no far jumps (i.e. BL) has been issued.
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// Undo the spill / restore of LR if possible.
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if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
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MadeChange |= UndoLRSpillRestore();
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BBSizes.clear();
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BBOffsets.clear();
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WaterList.clear();
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CPUsers.clear();
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CPEntries.clear();
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ImmBranches.clear();
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PushPopMIs.clear();
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T2JumpTables.clear();
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return MadeChange;
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}
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/// DoInitialPlacement - Perform the initial placement of the constant pool
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/// entries. To start with, we put them all at the end of the function.
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void ARMConstantIslands::DoInitialPlacement(MachineFunction &MF,
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std::vector<MachineInstr*> &CPEMIs) {
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// Create the basic block to hold the CPE's.
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MachineBasicBlock *BB = MF.CreateMachineBasicBlock();
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MF.push_back(BB);
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// Add all of the constants from the constant pool to the end block, use an
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// identity mapping of CPI's to CPE's.
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const std::vector<MachineConstantPoolEntry> &CPs =
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MF.getConstantPool()->getConstants();
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const TargetData &TD = *MF.getTarget().getTargetData();
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for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
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unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
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// Verify that all constant pool entries are a multiple of 4 bytes. If not,
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// we would have to pad them out or something so that instructions stay
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// aligned.
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assert((Size & 3) == 0 && "CP Entry not multiple of 4 bytes!");
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MachineInstr *CPEMI =
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BuildMI(BB, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
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.addImm(i).addConstantPoolIndex(i).addImm(Size);
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CPEMIs.push_back(CPEMI);
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// Add a new CPEntry, but no corresponding CPUser yet.
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std::vector<CPEntry> CPEs;
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CPEs.push_back(CPEntry(CPEMI, i));
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CPEntries.push_back(CPEs);
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NumCPEs++;
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DEBUG(errs() << "Moved CPI#" << i << " to end of function as #" << i
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<< "\n");
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}
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}
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/// BBHasFallthrough - Return true if the specified basic block can fallthrough
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/// into the block immediately after it.
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static bool BBHasFallthrough(MachineBasicBlock *MBB) {
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// Get the next machine basic block in the function.
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MachineFunction::iterator MBBI = MBB;
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if (llvm::next(MBBI) == MBB->getParent()->end()) // Can't fall off end of function.
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return false;
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MachineBasicBlock *NextBB = llvm::next(MBBI);
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for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
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E = MBB->succ_end(); I != E; ++I)
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if (*I == NextBB)
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return true;
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return false;
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}
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/// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
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/// look up the corresponding CPEntry.
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ARMConstantIslands::CPEntry
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*ARMConstantIslands::findConstPoolEntry(unsigned CPI,
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const MachineInstr *CPEMI) {
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std::vector<CPEntry> &CPEs = CPEntries[CPI];
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// Number of entries per constpool index should be small, just do a
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// linear search.
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for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
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if (CPEs[i].CPEMI == CPEMI)
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return &CPEs[i];
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}
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return NULL;
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}
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/// JumpTableFunctionScan - Do a scan of the function, building up
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/// information about the sizes of each block and the locations of all
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/// the jump tables.
|
|
void ARMConstantIslands::JumpTableFunctionScan(MachineFunction &MF) {
|
|
for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
|
|
MBBI != E; ++MBBI) {
|
|
MachineBasicBlock &MBB = *MBBI;
|
|
|
|
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
|
|
I != E; ++I)
|
|
if (I->getDesc().isBranch() && I->getOpcode() == ARM::t2BR_JT)
|
|
T2JumpTables.push_back(I);
|
|
}
|
|
}
|
|
|
|
/// InitialFunctionScan - Do the initial scan of the function, building up
|
|
/// information about the sizes of each block, the location of all the water,
|
|
/// and finding all of the constant pool users.
|
|
void ARMConstantIslands::InitialFunctionScan(MachineFunction &MF,
|
|
const std::vector<MachineInstr*> &CPEMIs) {
|
|
// First thing, see if the function has any inline assembly in it. If so,
|
|
// we have to be conservative about alignment assumptions, as we don't
|
|
// know for sure the size of any instructions in the inline assembly.
|
|
for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
|
|
MBBI != E; ++MBBI) {
|
|
MachineBasicBlock &MBB = *MBBI;
|
|
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
|
|
I != E; ++I)
|
|
if (I->getOpcode() == ARM::INLINEASM)
|
|
HasInlineAsm = true;
|
|
}
|
|
|
|
// Now go back through the instructions and build up our data structures
|
|
unsigned Offset = 0;
|
|
for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
|
|
MBBI != E; ++MBBI) {
|
|
MachineBasicBlock &MBB = *MBBI;
|
|
|
|
// If this block doesn't fall through into the next MBB, then this is
|
|
// 'water' that a constant pool island could be placed.
|
|
if (!BBHasFallthrough(&MBB))
|
|
WaterList.push_back(&MBB);
|
|
|
|
unsigned MBBSize = 0;
|
|
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
|
|
I != E; ++I) {
|
|
// Add instruction size to MBBSize.
|
|
MBBSize += TII->GetInstSizeInBytes(I);
|
|
|
|
int Opc = I->getOpcode();
|
|
if (I->getDesc().isBranch()) {
|
|
bool isCond = false;
|
|
unsigned Bits = 0;
|
|
unsigned Scale = 1;
|
|
int UOpc = Opc;
|
|
switch (Opc) {
|
|
default:
|
|
continue; // Ignore other JT branches
|
|
case ARM::tBR_JTr:
|
|
// A Thumb1 table jump may involve padding; for the offsets to
|
|
// be right, functions containing these must be 4-byte aligned.
|
|
MF.EnsureAlignment(2U);
|
|
if ((Offset+MBBSize)%4 != 0 || HasInlineAsm)
|
|
// FIXME: Add a pseudo ALIGN instruction instead.
|
|
MBBSize += 2; // padding
|
|
continue; // Does not get an entry in ImmBranches
|
|
case ARM::t2BR_JT:
|
|
T2JumpTables.push_back(I);
|
|
continue; // Does not get an entry in ImmBranches
|
|
case ARM::Bcc:
|
|
isCond = true;
|
|
UOpc = ARM::B;
|
|
// Fallthrough
|
|
case ARM::B:
|
|
Bits = 24;
|
|
Scale = 4;
|
|
break;
|
|
case ARM::tBcc:
|
|
isCond = true;
|
|
UOpc = ARM::tB;
|
|
Bits = 8;
|
|
Scale = 2;
|
|
break;
|
|
case ARM::tB:
|
|
Bits = 11;
|
|
Scale = 2;
|
|
break;
|
|
case ARM::t2Bcc:
|
|
isCond = true;
|
|
UOpc = ARM::t2B;
|
|
Bits = 20;
|
|
Scale = 2;
|
|
break;
|
|
case ARM::t2B:
|
|
Bits = 24;
|
|
Scale = 2;
|
|
break;
|
|
}
|
|
|
|
// Record this immediate branch.
|
|
unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
|
|
ImmBranches.push_back(ImmBranch(I, MaxOffs, isCond, UOpc));
|
|
}
|
|
|
|
if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
|
|
PushPopMIs.push_back(I);
|
|
|
|
if (Opc == ARM::CONSTPOOL_ENTRY)
|
|
continue;
|
|
|
|
// Scan the instructions for constant pool operands.
|
|
for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op)
|
|
if (I->getOperand(op).isCPI()) {
|
|
// We found one. The addressing mode tells us the max displacement
|
|
// from the PC that this instruction permits.
|
|
|
|
// Basic size info comes from the TSFlags field.
|
|
unsigned Bits = 0;
|
|
unsigned Scale = 1;
|
|
bool NegOk = false;
|
|
bool IsSoImm = false;
|
|
|
|
switch (Opc) {
|
|
default:
|
|
llvm_unreachable("Unknown addressing mode for CP reference!");
|
|
break;
|
|
|
|
// Taking the address of a CP entry.
|
|
case ARM::LEApcrel:
|
|
// This takes a SoImm, which is 8 bit immediate rotated. We'll
|
|
// pretend the maximum offset is 255 * 4. Since each instruction
|
|
// 4 byte wide, this is always correct. We'll check for other
|
|
// displacements that fits in a SoImm as well.
|
|
Bits = 8;
|
|
Scale = 4;
|
|
NegOk = true;
|
|
IsSoImm = true;
|
|
break;
|
|
case ARM::t2LEApcrel:
|
|
Bits = 12;
|
|
NegOk = true;
|
|
break;
|
|
case ARM::tLEApcrel:
|
|
Bits = 8;
|
|
Scale = 4;
|
|
break;
|
|
|
|
case ARM::LDR:
|
|
case ARM::LDRcp:
|
|
case ARM::t2LDRpci:
|
|
Bits = 12; // +-offset_12
|
|
NegOk = true;
|
|
break;
|
|
|
|
case ARM::tLDRpci:
|
|
case ARM::tLDRcp:
|
|
Bits = 8;
|
|
Scale = 4; // +(offset_8*4)
|
|
break;
|
|
|
|
case ARM::VLDRD:
|
|
case ARM::VLDRS:
|
|
Bits = 8;
|
|
Scale = 4; // +-(offset_8*4)
|
|
NegOk = true;
|
|
break;
|
|
}
|
|
|
|
// Remember that this is a user of a CP entry.
|
|
unsigned CPI = I->getOperand(op).getIndex();
|
|
MachineInstr *CPEMI = CPEMIs[CPI];
|
|
unsigned MaxOffs = ((1 << Bits)-1) * Scale;
|
|
CPUsers.push_back(CPUser(I, CPEMI, MaxOffs, NegOk, IsSoImm));
|
|
|
|
// Increment corresponding CPEntry reference count.
|
|
CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
|
|
assert(CPE && "Cannot find a corresponding CPEntry!");
|
|
CPE->RefCount++;
|
|
|
|
// Instructions can only use one CP entry, don't bother scanning the
|
|
// rest of the operands.
|
|
break;
|
|
}
|
|
}
|
|
|
|
// In thumb mode, if this block is a constpool island, we may need padding
|
|
// so it's aligned on 4 byte boundary.
|
|
if (isThumb &&
|
|
!MBB.empty() &&
|
|
MBB.begin()->getOpcode() == ARM::CONSTPOOL_ENTRY &&
|
|
((Offset%4) != 0 || HasInlineAsm))
|
|
MBBSize += 2;
|
|
|
|
BBSizes.push_back(MBBSize);
|
|
BBOffsets.push_back(Offset);
|
|
Offset += MBBSize;
|
|
}
|
|
}
|
|
|
|
/// GetOffsetOf - Return the current offset of the specified machine instruction
|
|
/// from the start of the function. This offset changes as stuff is moved
|
|
/// around inside the function.
|
|
unsigned ARMConstantIslands::GetOffsetOf(MachineInstr *MI) const {
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
|
|
// The offset is composed of two things: the sum of the sizes of all MBB's
|
|
// before this instruction's block, and the offset from the start of the block
|
|
// it is in.
|
|
unsigned Offset = BBOffsets[MBB->getNumber()];
|
|
|
|
// If we're looking for a CONSTPOOL_ENTRY in Thumb, see if this block has
|
|
// alignment padding, and compensate if so.
|
|
if (isThumb &&
|
|
MI->getOpcode() == ARM::CONSTPOOL_ENTRY &&
|
|
(Offset%4 != 0 || HasInlineAsm))
|
|
Offset += 2;
|
|
|
|
// Sum instructions before MI in MBB.
|
|
for (MachineBasicBlock::iterator I = MBB->begin(); ; ++I) {
|
|
assert(I != MBB->end() && "Didn't find MI in its own basic block?");
|
|
if (&*I == MI) return Offset;
|
|
Offset += TII->GetInstSizeInBytes(I);
|
|
}
|
|
}
|
|
|
|
/// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
|
|
/// ID.
|
|
static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
|
|
const MachineBasicBlock *RHS) {
|
|
return LHS->getNumber() < RHS->getNumber();
|
|
}
|
|
|
|
/// UpdateForInsertedWaterBlock - When a block is newly inserted into the
|
|
/// machine function, it upsets all of the block numbers. Renumber the blocks
|
|
/// and update the arrays that parallel this numbering.
|
|
void ARMConstantIslands::UpdateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
|
|
// Renumber the MBB's to keep them consequtive.
|
|
NewBB->getParent()->RenumberBlocks(NewBB);
|
|
|
|
// Insert a size into BBSizes to align it properly with the (newly
|
|
// renumbered) block numbers.
|
|
BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
|
|
|
|
// Likewise for BBOffsets.
|
|
BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
|
|
|
|
// Next, update WaterList. Specifically, we need to add NewMBB as having
|
|
// available water after it.
|
|
water_iterator IP =
|
|
std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
|
|
CompareMBBNumbers);
|
|
WaterList.insert(IP, NewBB);
|
|
}
|
|
|
|
|
|
/// Split the basic block containing MI into two blocks, which are joined by
|
|
/// an unconditional branch. Update data structures and renumber blocks to
|
|
/// account for this change and returns the newly created block.
|
|
MachineBasicBlock *ARMConstantIslands::SplitBlockBeforeInstr(MachineInstr *MI) {
|
|
MachineBasicBlock *OrigBB = MI->getParent();
|
|
MachineFunction &MF = *OrigBB->getParent();
|
|
|
|
// Create a new MBB for the code after the OrigBB.
|
|
MachineBasicBlock *NewBB =
|
|
MF.CreateMachineBasicBlock(OrigBB->getBasicBlock());
|
|
MachineFunction::iterator MBBI = OrigBB; ++MBBI;
|
|
MF.insert(MBBI, NewBB);
|
|
|
|
// Splice the instructions starting with MI over to NewBB.
|
|
NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
|
|
|
|
// Add an unconditional branch from OrigBB to NewBB.
|
|
// Note the new unconditional branch is not being recorded.
|
|
// There doesn't seem to be meaningful DebugInfo available; this doesn't
|
|
// correspond to anything in the source.
|
|
unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
|
|
BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
|
|
NumSplit++;
|
|
|
|
// Update the CFG. All succs of OrigBB are now succs of NewBB.
|
|
while (!OrigBB->succ_empty()) {
|
|
MachineBasicBlock *Succ = *OrigBB->succ_begin();
|
|
OrigBB->removeSuccessor(Succ);
|
|
NewBB->addSuccessor(Succ);
|
|
|
|
// This pass should be run after register allocation, so there should be no
|
|
// PHI nodes to update.
|
|
assert((Succ->empty() || !Succ->begin()->isPHI())
|
|
&& "PHI nodes should be eliminated by now!");
|
|
}
|
|
|
|
// OrigBB branches to NewBB.
|
|
OrigBB->addSuccessor(NewBB);
|
|
|
|
// Update internal data structures to account for the newly inserted MBB.
|
|
// This is almost the same as UpdateForInsertedWaterBlock, except that
|
|
// the Water goes after OrigBB, not NewBB.
|
|
MF.RenumberBlocks(NewBB);
|
|
|
|
// Insert a size into BBSizes to align it properly with the (newly
|
|
// renumbered) block numbers.
|
|
BBSizes.insert(BBSizes.begin()+NewBB->getNumber(), 0);
|
|
|
|
// Likewise for BBOffsets.
|
|
BBOffsets.insert(BBOffsets.begin()+NewBB->getNumber(), 0);
|
|
|
|
// Next, update WaterList. Specifically, we need to add OrigMBB as having
|
|
// available water after it (but not if it's already there, which happens
|
|
// when splitting before a conditional branch that is followed by an
|
|
// unconditional branch - in that case we want to insert NewBB).
|
|
water_iterator IP =
|
|
std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
|
|
CompareMBBNumbers);
|
|
MachineBasicBlock* WaterBB = *IP;
|
|
if (WaterBB == OrigBB)
|
|
WaterList.insert(llvm::next(IP), NewBB);
|
|
else
|
|
WaterList.insert(IP, OrigBB);
|
|
NewWaterList.insert(OrigBB);
|
|
|
|
// Figure out how large the first NewMBB is. (It cannot
|
|
// contain a constpool_entry or tablejump.)
|
|
unsigned NewBBSize = 0;
|
|
for (MachineBasicBlock::iterator I = NewBB->begin(), E = NewBB->end();
|
|
I != E; ++I)
|
|
NewBBSize += TII->GetInstSizeInBytes(I);
|
|
|
|
unsigned OrigBBI = OrigBB->getNumber();
|
|
unsigned NewBBI = NewBB->getNumber();
|
|
// Set the size of NewBB in BBSizes.
|
|
BBSizes[NewBBI] = NewBBSize;
|
|
|
|
// We removed instructions from UserMBB, subtract that off from its size.
|
|
// Add 2 or 4 to the block to count the unconditional branch we added to it.
|
|
int delta = isThumb1 ? 2 : 4;
|
|
BBSizes[OrigBBI] -= NewBBSize - delta;
|
|
|
|
// ...and adjust BBOffsets for NewBB accordingly.
|
|
BBOffsets[NewBBI] = BBOffsets[OrigBBI] + BBSizes[OrigBBI];
|
|
|
|
// All BBOffsets following these blocks must be modified.
|
|
AdjustBBOffsetsAfter(NewBB, delta);
|
|
|
|
return NewBB;
|
|
}
|
|
|
|
/// OffsetIsInRange - Checks whether UserOffset (the location of a constant pool
|
|
/// reference) is within MaxDisp of TrialOffset (a proposed location of a
|
|
/// constant pool entry).
|
|
bool ARMConstantIslands::OffsetIsInRange(unsigned UserOffset,
|
|
unsigned TrialOffset, unsigned MaxDisp,
|
|
bool NegativeOK, bool IsSoImm) {
|
|
// On Thumb offsets==2 mod 4 are rounded down by the hardware for
|
|
// purposes of the displacement computation; compensate for that here.
|
|
// Effectively, the valid range of displacements is 2 bytes smaller for such
|
|
// references.
|
|
unsigned TotalAdj = 0;
|
|
if (isThumb && UserOffset%4 !=0) {
|
|
UserOffset -= 2;
|
|
TotalAdj = 2;
|
|
}
|
|
// CPEs will be rounded up to a multiple of 4.
|
|
if (isThumb && TrialOffset%4 != 0) {
|
|
TrialOffset += 2;
|
|
TotalAdj += 2;
|
|
}
|
|
|
|
// In Thumb2 mode, later branch adjustments can shift instructions up and
|
|
// cause alignment change. In the worst case scenario this can cause the
|
|
// user's effective address to be subtracted by 2 and the CPE's address to
|
|
// be plus 2.
|
|
if (isThumb2 && TotalAdj != 4)
|
|
MaxDisp -= (4 - TotalAdj);
|
|
|
|
if (UserOffset <= TrialOffset) {
|
|
// User before the Trial.
|
|
if (TrialOffset - UserOffset <= MaxDisp)
|
|
return true;
|
|
// FIXME: Make use full range of soimm values.
|
|
} else if (NegativeOK) {
|
|
if (UserOffset - TrialOffset <= MaxDisp)
|
|
return true;
|
|
// FIXME: Make use full range of soimm values.
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// WaterIsInRange - Returns true if a CPE placed after the specified
|
|
/// Water (a basic block) will be in range for the specific MI.
|
|
|
|
bool ARMConstantIslands::WaterIsInRange(unsigned UserOffset,
|
|
MachineBasicBlock* Water, CPUser &U) {
|
|
unsigned MaxDisp = U.MaxDisp;
|
|
unsigned CPEOffset = BBOffsets[Water->getNumber()] +
|
|
BBSizes[Water->getNumber()];
|
|
|
|
// If the CPE is to be inserted before the instruction, that will raise
|
|
// the offset of the instruction.
|
|
if (CPEOffset < UserOffset)
|
|
UserOffset += U.CPEMI->getOperand(2).getImm();
|
|
|
|
return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, U.NegOk, U.IsSoImm);
|
|
}
|
|
|
|
/// CPEIsInRange - Returns true if the distance between specific MI and
|
|
/// specific ConstPool entry instruction can fit in MI's displacement field.
|
|
bool ARMConstantIslands::CPEIsInRange(MachineInstr *MI, unsigned UserOffset,
|
|
MachineInstr *CPEMI, unsigned MaxDisp,
|
|
bool NegOk, bool DoDump) {
|
|
unsigned CPEOffset = GetOffsetOf(CPEMI);
|
|
assert((CPEOffset%4 == 0 || HasInlineAsm) && "Misaligned CPE");
|
|
|
|
if (DoDump) {
|
|
DEBUG(errs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
|
|
<< " max delta=" << MaxDisp
|
|
<< " insn address=" << UserOffset
|
|
<< " CPE address=" << CPEOffset
|
|
<< " offset=" << int(CPEOffset-UserOffset) << "\t" << *MI);
|
|
}
|
|
|
|
return OffsetIsInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
/// BBIsJumpedOver - Return true of the specified basic block's only predecessor
|
|
/// unconditionally branches to its only successor.
|
|
static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
|
|
if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
|
|
return false;
|
|
|
|
MachineBasicBlock *Succ = *MBB->succ_begin();
|
|
MachineBasicBlock *Pred = *MBB->pred_begin();
|
|
MachineInstr *PredMI = &Pred->back();
|
|
if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
|
|
|| PredMI->getOpcode() == ARM::t2B)
|
|
return PredMI->getOperand(0).getMBB() == Succ;
|
|
return false;
|
|
}
|
|
#endif // NDEBUG
|
|
|
|
void ARMConstantIslands::AdjustBBOffsetsAfter(MachineBasicBlock *BB,
|
|
int delta) {
|
|
MachineFunction::iterator MBBI = BB; MBBI = llvm::next(MBBI);
|
|
for(unsigned i = BB->getNumber()+1, e = BB->getParent()->getNumBlockIDs();
|
|
i < e; ++i) {
|
|
BBOffsets[i] += delta;
|
|
// If some existing blocks have padding, adjust the padding as needed, a
|
|
// bit tricky. delta can be negative so don't use % on that.
|
|
if (!isThumb)
|
|
continue;
|
|
MachineBasicBlock *MBB = MBBI;
|
|
if (!MBB->empty() && !HasInlineAsm) {
|
|
// Constant pool entries require padding.
|
|
if (MBB->begin()->getOpcode() == ARM::CONSTPOOL_ENTRY) {
|
|
unsigned OldOffset = BBOffsets[i] - delta;
|
|
if ((OldOffset%4) == 0 && (BBOffsets[i]%4) != 0) {
|
|
// add new padding
|
|
BBSizes[i] += 2;
|
|
delta += 2;
|
|
} else if ((OldOffset%4) != 0 && (BBOffsets[i]%4) == 0) {
|
|
// remove existing padding
|
|
BBSizes[i] -= 2;
|
|
delta -= 2;
|
|
}
|
|
}
|
|
// Thumb1 jump tables require padding. They should be at the end;
|
|
// following unconditional branches are removed by AnalyzeBranch.
|
|
MachineInstr *ThumbJTMI = prior(MBB->end());
|
|
if (ThumbJTMI->getOpcode() == ARM::tBR_JTr) {
|
|
unsigned NewMIOffset = GetOffsetOf(ThumbJTMI);
|
|
unsigned OldMIOffset = NewMIOffset - delta;
|
|
if ((OldMIOffset%4) == 0 && (NewMIOffset%4) != 0) {
|
|
// remove existing padding
|
|
BBSizes[i] -= 2;
|
|
delta -= 2;
|
|
} else if ((OldMIOffset%4) != 0 && (NewMIOffset%4) == 0) {
|
|
// add new padding
|
|
BBSizes[i] += 2;
|
|
delta += 2;
|
|
}
|
|
}
|
|
if (delta==0)
|
|
return;
|
|
}
|
|
MBBI = llvm::next(MBBI);
|
|
}
|
|
}
|
|
|
|
/// DecrementOldEntry - find the constant pool entry with index CPI
|
|
/// and instruction CPEMI, and decrement its refcount. If the refcount
|
|
/// becomes 0 remove the entry and instruction. Returns true if we removed
|
|
/// the entry, false if we didn't.
|
|
|
|
bool ARMConstantIslands::DecrementOldEntry(unsigned CPI, MachineInstr *CPEMI) {
|
|
// Find the old entry. Eliminate it if it is no longer used.
|
|
CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
|
|
assert(CPE && "Unexpected!");
|
|
if (--CPE->RefCount == 0) {
|
|
RemoveDeadCPEMI(CPEMI);
|
|
CPE->CPEMI = NULL;
|
|
NumCPEs--;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// LookForCPEntryInRange - see if the currently referenced CPE is in range;
|
|
/// if not, see if an in-range clone of the CPE is in range, and if so,
|
|
/// change the data structures so the user references the clone. Returns:
|
|
/// 0 = no existing entry found
|
|
/// 1 = entry found, and there were no code insertions or deletions
|
|
/// 2 = entry found, and there were code insertions or deletions
|
|
int ARMConstantIslands::LookForExistingCPEntry(CPUser& U, unsigned UserOffset)
|
|
{
|
|
MachineInstr *UserMI = U.MI;
|
|
MachineInstr *CPEMI = U.CPEMI;
|
|
|
|
// Check to see if the CPE is already in-range.
|
|
if (CPEIsInRange(UserMI, UserOffset, CPEMI, U.MaxDisp, U.NegOk, true)) {
|
|
DEBUG(errs() << "In range\n");
|
|
return 1;
|
|
}
|
|
|
|
// No. Look for previously created clones of the CPE that are in range.
|
|
unsigned CPI = CPEMI->getOperand(1).getIndex();
|
|
std::vector<CPEntry> &CPEs = CPEntries[CPI];
|
|
for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
|
|
// We already tried this one
|
|
if (CPEs[i].CPEMI == CPEMI)
|
|
continue;
|
|
// Removing CPEs can leave empty entries, skip
|
|
if (CPEs[i].CPEMI == NULL)
|
|
continue;
|
|
if (CPEIsInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.MaxDisp, U.NegOk)) {
|
|
DEBUG(errs() << "Replacing CPE#" << CPI << " with CPE#"
|
|
<< CPEs[i].CPI << "\n");
|
|
// Point the CPUser node to the replacement
|
|
U.CPEMI = CPEs[i].CPEMI;
|
|
// Change the CPI in the instruction operand to refer to the clone.
|
|
for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
|
|
if (UserMI->getOperand(j).isCPI()) {
|
|
UserMI->getOperand(j).setIndex(CPEs[i].CPI);
|
|
break;
|
|
}
|
|
// Adjust the refcount of the clone...
|
|
CPEs[i].RefCount++;
|
|
// ...and the original. If we didn't remove the old entry, none of the
|
|
// addresses changed, so we don't need another pass.
|
|
return DecrementOldEntry(CPI, CPEMI) ? 2 : 1;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
|
|
/// the specific unconditional branch instruction.
|
|
static inline unsigned getUnconditionalBrDisp(int Opc) {
|
|
switch (Opc) {
|
|
case ARM::tB:
|
|
return ((1<<10)-1)*2;
|
|
case ARM::t2B:
|
|
return ((1<<23)-1)*2;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ((1<<23)-1)*4;
|
|
}
|
|
|
|
/// LookForWater - Look for an existing entry in the WaterList in which
|
|
/// we can place the CPE referenced from U so it's within range of U's MI.
|
|
/// Returns true if found, false if not. If it returns true, WaterIter
|
|
/// is set to the WaterList entry. For Thumb, prefer water that will not
|
|
/// introduce padding to water that will. To ensure that this pass
|
|
/// terminates, the CPE location for a particular CPUser is only allowed to
|
|
/// move to a lower address, so search backward from the end of the list and
|
|
/// prefer the first water that is in range.
|
|
bool ARMConstantIslands::LookForWater(CPUser &U, unsigned UserOffset,
|
|
water_iterator &WaterIter) {
|
|
if (WaterList.empty())
|
|
return false;
|
|
|
|
bool FoundWaterThatWouldPad = false;
|
|
water_iterator IPThatWouldPad;
|
|
for (water_iterator IP = prior(WaterList.end()),
|
|
B = WaterList.begin();; --IP) {
|
|
MachineBasicBlock* WaterBB = *IP;
|
|
// Check if water is in range and is either at a lower address than the
|
|
// current "high water mark" or a new water block that was created since
|
|
// the previous iteration by inserting an unconditional branch. In the
|
|
// latter case, we want to allow resetting the high water mark back to
|
|
// this new water since we haven't seen it before. Inserting branches
|
|
// should be relatively uncommon and when it does happen, we want to be
|
|
// sure to take advantage of it for all the CPEs near that block, so that
|
|
// we don't insert more branches than necessary.
|
|
if (WaterIsInRange(UserOffset, WaterBB, U) &&
|
|
(WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
|
|
NewWaterList.count(WaterBB))) {
|
|
unsigned WBBId = WaterBB->getNumber();
|
|
if (isThumb &&
|
|
(BBOffsets[WBBId] + BBSizes[WBBId])%4 != 0) {
|
|
// This is valid Water, but would introduce padding. Remember
|
|
// it in case we don't find any Water that doesn't do this.
|
|
if (!FoundWaterThatWouldPad) {
|
|
FoundWaterThatWouldPad = true;
|
|
IPThatWouldPad = IP;
|
|
}
|
|
} else {
|
|
WaterIter = IP;
|
|
return true;
|
|
}
|
|
}
|
|
if (IP == B)
|
|
break;
|
|
}
|
|
if (FoundWaterThatWouldPad) {
|
|
WaterIter = IPThatWouldPad;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// CreateNewWater - No existing WaterList entry will work for
|
|
/// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
|
|
/// block is used if in range, and the conditional branch munged so control
|
|
/// flow is correct. Otherwise the block is split to create a hole with an
|
|
/// unconditional branch around it. In either case NewMBB is set to a
|
|
/// block following which the new island can be inserted (the WaterList
|
|
/// is not adjusted).
|
|
void ARMConstantIslands::CreateNewWater(unsigned CPUserIndex,
|
|
unsigned UserOffset,
|
|
MachineBasicBlock *&NewMBB) {
|
|
CPUser &U = CPUsers[CPUserIndex];
|
|
MachineInstr *UserMI = U.MI;
|
|
MachineInstr *CPEMI = U.CPEMI;
|
|
MachineBasicBlock *UserMBB = UserMI->getParent();
|
|
unsigned OffsetOfNextBlock = BBOffsets[UserMBB->getNumber()] +
|
|
BBSizes[UserMBB->getNumber()];
|
|
assert(OffsetOfNextBlock== BBOffsets[UserMBB->getNumber()+1]);
|
|
|
|
// If the block does not end in an unconditional branch already, and if the
|
|
// end of the block is within range, make new water there. (The addition
|
|
// below is for the unconditional branch we will be adding: 4 bytes on ARM +
|
|
// Thumb2, 2 on Thumb1. Possible Thumb1 alignment padding is allowed for
|
|
// inside OffsetIsInRange.
|
|
if (BBHasFallthrough(UserMBB) &&
|
|
OffsetIsInRange(UserOffset, OffsetOfNextBlock + (isThumb1 ? 2: 4),
|
|
U.MaxDisp, U.NegOk, U.IsSoImm)) {
|
|
DEBUG(errs() << "Split at end of block\n");
|
|
if (&UserMBB->back() == UserMI)
|
|
assert(BBHasFallthrough(UserMBB) && "Expected a fallthrough BB!");
|
|
NewMBB = llvm::next(MachineFunction::iterator(UserMBB));
|
|
// Add an unconditional branch from UserMBB to fallthrough block.
|
|
// Record it for branch lengthening; this new branch will not get out of
|
|
// range, but if the preceding conditional branch is out of range, the
|
|
// targets will be exchanged, and the altered branch may be out of
|
|
// range, so the machinery has to know about it.
|
|
int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
|
|
BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
|
|
unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
|
|
ImmBranches.push_back(ImmBranch(&UserMBB->back(),
|
|
MaxDisp, false, UncondBr));
|
|
int delta = isThumb1 ? 2 : 4;
|
|
BBSizes[UserMBB->getNumber()] += delta;
|
|
AdjustBBOffsetsAfter(UserMBB, delta);
|
|
} else {
|
|
// What a big block. Find a place within the block to split it.
|
|
// This is a little tricky on Thumb1 since instructions are 2 bytes
|
|
// and constant pool entries are 4 bytes: if instruction I references
|
|
// island CPE, and instruction I+1 references CPE', it will
|
|
// not work well to put CPE as far forward as possible, since then
|
|
// CPE' cannot immediately follow it (that location is 2 bytes
|
|
// farther away from I+1 than CPE was from I) and we'd need to create
|
|
// a new island. So, we make a first guess, then walk through the
|
|
// instructions between the one currently being looked at and the
|
|
// possible insertion point, and make sure any other instructions
|
|
// that reference CPEs will be able to use the same island area;
|
|
// if not, we back up the insertion point.
|
|
|
|
// The 4 in the following is for the unconditional branch we'll be
|
|
// inserting (allows for long branch on Thumb1). Alignment of the
|
|
// island is handled inside OffsetIsInRange.
|
|
unsigned BaseInsertOffset = UserOffset + U.MaxDisp -4;
|
|
// This could point off the end of the block if we've already got
|
|
// constant pool entries following this block; only the last one is
|
|
// in the water list. Back past any possible branches (allow for a
|
|
// conditional and a maximally long unconditional).
|
|
if (BaseInsertOffset >= BBOffsets[UserMBB->getNumber()+1])
|
|
BaseInsertOffset = BBOffsets[UserMBB->getNumber()+1] -
|
|
(isThumb1 ? 6 : 8);
|
|
unsigned EndInsertOffset = BaseInsertOffset +
|
|
CPEMI->getOperand(2).getImm();
|
|
MachineBasicBlock::iterator MI = UserMI;
|
|
++MI;
|
|
unsigned CPUIndex = CPUserIndex+1;
|
|
for (unsigned Offset = UserOffset+TII->GetInstSizeInBytes(UserMI);
|
|
Offset < BaseInsertOffset;
|
|
Offset += TII->GetInstSizeInBytes(MI),
|
|
MI = llvm::next(MI)) {
|
|
if (CPUIndex < CPUsers.size() && CPUsers[CPUIndex].MI == MI) {
|
|
CPUser &U = CPUsers[CPUIndex];
|
|
if (!OffsetIsInRange(Offset, EndInsertOffset,
|
|
U.MaxDisp, U.NegOk, U.IsSoImm)) {
|
|
BaseInsertOffset -= (isThumb1 ? 2 : 4);
|
|
EndInsertOffset -= (isThumb1 ? 2 : 4);
|
|
}
|
|
// This is overly conservative, as we don't account for CPEMIs
|
|
// being reused within the block, but it doesn't matter much.
|
|
EndInsertOffset += CPUsers[CPUIndex].CPEMI->getOperand(2).getImm();
|
|
CPUIndex++;
|
|
}
|
|
}
|
|
DEBUG(errs() << "Split in middle of big block\n");
|
|
NewMBB = SplitBlockBeforeInstr(prior(MI));
|
|
}
|
|
}
|
|
|
|
/// HandleConstantPoolUser - Analyze the specified user, checking to see if it
|
|
/// is out-of-range. If so, pick up the constant pool value and move it some
|
|
/// place in-range. Return true if we changed any addresses (thus must run
|
|
/// another pass of branch lengthening), false otherwise.
|
|
bool ARMConstantIslands::HandleConstantPoolUser(MachineFunction &MF,
|
|
unsigned CPUserIndex) {
|
|
CPUser &U = CPUsers[CPUserIndex];
|
|
MachineInstr *UserMI = U.MI;
|
|
MachineInstr *CPEMI = U.CPEMI;
|
|
unsigned CPI = CPEMI->getOperand(1).getIndex();
|
|
unsigned Size = CPEMI->getOperand(2).getImm();
|
|
// Compute this only once, it's expensive. The 4 or 8 is the value the
|
|
// hardware keeps in the PC.
|
|
unsigned UserOffset = GetOffsetOf(UserMI) + (isThumb ? 4 : 8);
|
|
|
|
// See if the current entry is within range, or there is a clone of it
|
|
// in range.
|
|
int result = LookForExistingCPEntry(U, UserOffset);
|
|
if (result==1) return false;
|
|
else if (result==2) return true;
|
|
|
|
// No existing clone of this CPE is within range.
|
|
// We will be generating a new clone. Get a UID for it.
|
|
unsigned ID = AFI->createConstPoolEntryUId();
|
|
|
|
// Look for water where we can place this CPE.
|
|
MachineBasicBlock *NewIsland = MF.CreateMachineBasicBlock();
|
|
MachineBasicBlock *NewMBB;
|
|
water_iterator IP;
|
|
if (LookForWater(U, UserOffset, IP)) {
|
|
DEBUG(errs() << "found water in range\n");
|
|
MachineBasicBlock *WaterBB = *IP;
|
|
|
|
// If the original WaterList entry was "new water" on this iteration,
|
|
// propagate that to the new island. This is just keeping NewWaterList
|
|
// updated to match the WaterList, which will be updated below.
|
|
if (NewWaterList.count(WaterBB)) {
|
|
NewWaterList.erase(WaterBB);
|
|
NewWaterList.insert(NewIsland);
|
|
}
|
|
// The new CPE goes before the following block (NewMBB).
|
|
NewMBB = llvm::next(MachineFunction::iterator(WaterBB));
|
|
|
|
} else {
|
|
// No water found.
|
|
DEBUG(errs() << "No water found\n");
|
|
CreateNewWater(CPUserIndex, UserOffset, NewMBB);
|
|
|
|
// SplitBlockBeforeInstr adds to WaterList, which is important when it is
|
|
// called while handling branches so that the water will be seen on the
|
|
// next iteration for constant pools, but in this context, we don't want
|
|
// it. Check for this so it will be removed from the WaterList.
|
|
// Also remove any entry from NewWaterList.
|
|
MachineBasicBlock *WaterBB = prior(MachineFunction::iterator(NewMBB));
|
|
IP = std::find(WaterList.begin(), WaterList.end(), WaterBB);
|
|
if (IP != WaterList.end())
|
|
NewWaterList.erase(WaterBB);
|
|
|
|
// We are adding new water. Update NewWaterList.
|
|
NewWaterList.insert(NewIsland);
|
|
}
|
|
|
|
// Remove the original WaterList entry; we want subsequent insertions in
|
|
// this vicinity to go after the one we're about to insert. This
|
|
// considerably reduces the number of times we have to move the same CPE
|
|
// more than once and is also important to ensure the algorithm terminates.
|
|
if (IP != WaterList.end())
|
|
WaterList.erase(IP);
|
|
|
|
// Okay, we know we can put an island before NewMBB now, do it!
|
|
MF.insert(NewMBB, NewIsland);
|
|
|
|
// Update internal data structures to account for the newly inserted MBB.
|
|
UpdateForInsertedWaterBlock(NewIsland);
|
|
|
|
// Decrement the old entry, and remove it if refcount becomes 0.
|
|
DecrementOldEntry(CPI, CPEMI);
|
|
|
|
// Now that we have an island to add the CPE to, clone the original CPE and
|
|
// add it to the island.
|
|
U.HighWaterMark = NewIsland;
|
|
U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
|
|
.addImm(ID).addConstantPoolIndex(CPI).addImm(Size);
|
|
CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
|
|
NumCPEs++;
|
|
|
|
BBOffsets[NewIsland->getNumber()] = BBOffsets[NewMBB->getNumber()];
|
|
// Compensate for .align 2 in thumb mode.
|
|
if (isThumb && (BBOffsets[NewIsland->getNumber()]%4 != 0 || HasInlineAsm))
|
|
Size += 2;
|
|
// Increase the size of the island block to account for the new entry.
|
|
BBSizes[NewIsland->getNumber()] += Size;
|
|
AdjustBBOffsetsAfter(NewIsland, Size);
|
|
|
|
// Finally, change the CPI in the instruction operand to be ID.
|
|
for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
|
|
if (UserMI->getOperand(i).isCPI()) {
|
|
UserMI->getOperand(i).setIndex(ID);
|
|
break;
|
|
}
|
|
|
|
DEBUG(errs() << " Moved CPE to #" << ID << " CPI=" << CPI
|
|
<< '\t' << *UserMI);
|
|
|
|
return true;
|
|
}
|
|
|
|
/// RemoveDeadCPEMI - Remove a dead constant pool entry instruction. Update
|
|
/// sizes and offsets of impacted basic blocks.
|
|
void ARMConstantIslands::RemoveDeadCPEMI(MachineInstr *CPEMI) {
|
|
MachineBasicBlock *CPEBB = CPEMI->getParent();
|
|
unsigned Size = CPEMI->getOperand(2).getImm();
|
|
CPEMI->eraseFromParent();
|
|
BBSizes[CPEBB->getNumber()] -= Size;
|
|
// All succeeding offsets have the current size value added in, fix this.
|
|
if (CPEBB->empty()) {
|
|
// In thumb1 mode, the size of island may be padded by two to compensate for
|
|
// the alignment requirement. Then it will now be 2 when the block is
|
|
// empty, so fix this.
|
|
// All succeeding offsets have the current size value added in, fix this.
|
|
if (BBSizes[CPEBB->getNumber()] != 0) {
|
|
Size += BBSizes[CPEBB->getNumber()];
|
|
BBSizes[CPEBB->getNumber()] = 0;
|
|
}
|
|
}
|
|
AdjustBBOffsetsAfter(CPEBB, -Size);
|
|
// An island has only one predecessor BB and one successor BB. Check if
|
|
// this BB's predecessor jumps directly to this BB's successor. This
|
|
// shouldn't happen currently.
|
|
assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
|
|
// FIXME: remove the empty blocks after all the work is done?
|
|
}
|
|
|
|
/// RemoveUnusedCPEntries - Remove constant pool entries whose refcounts
|
|
/// are zero.
|
|
bool ARMConstantIslands::RemoveUnusedCPEntries() {
|
|
unsigned MadeChange = false;
|
|
for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
|
|
std::vector<CPEntry> &CPEs = CPEntries[i];
|
|
for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
|
|
if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
|
|
RemoveDeadCPEMI(CPEs[j].CPEMI);
|
|
CPEs[j].CPEMI = NULL;
|
|
MadeChange = true;
|
|
}
|
|
}
|
|
}
|
|
return MadeChange;
|
|
}
|
|
|
|
/// BBIsInRange - Returns true if the distance between specific MI and
|
|
/// specific BB can fit in MI's displacement field.
|
|
bool ARMConstantIslands::BBIsInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
|
|
unsigned MaxDisp) {
|
|
unsigned PCAdj = isThumb ? 4 : 8;
|
|
unsigned BrOffset = GetOffsetOf(MI) + PCAdj;
|
|
unsigned DestOffset = BBOffsets[DestBB->getNumber()];
|
|
|
|
DEBUG(errs() << "Branch of destination BB#" << DestBB->getNumber()
|
|
<< " from BB#" << MI->getParent()->getNumber()
|
|
<< " max delta=" << MaxDisp
|
|
<< " from " << GetOffsetOf(MI) << " to " << DestOffset
|
|
<< " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
|
|
|
|
if (BrOffset <= DestOffset) {
|
|
// Branch before the Dest.
|
|
if (DestOffset-BrOffset <= MaxDisp)
|
|
return true;
|
|
} else {
|
|
if (BrOffset-DestOffset <= MaxDisp)
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// FixUpImmediateBr - Fix up an immediate branch whose destination is too far
|
|
/// away to fit in its displacement field.
|
|
bool ARMConstantIslands::FixUpImmediateBr(MachineFunction &MF, ImmBranch &Br) {
|
|
MachineInstr *MI = Br.MI;
|
|
MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
|
|
|
|
// Check to see if the DestBB is already in-range.
|
|
if (BBIsInRange(MI, DestBB, Br.MaxDisp))
|
|
return false;
|
|
|
|
if (!Br.isCond)
|
|
return FixUpUnconditionalBr(MF, Br);
|
|
return FixUpConditionalBr(MF, Br);
|
|
}
|
|
|
|
/// FixUpUnconditionalBr - Fix up an unconditional branch whose destination is
|
|
/// too far away to fit in its displacement field. If the LR register has been
|
|
/// spilled in the epilogue, then we can use BL to implement a far jump.
|
|
/// Otherwise, add an intermediate branch instruction to a branch.
|
|
bool
|
|
ARMConstantIslands::FixUpUnconditionalBr(MachineFunction &MF, ImmBranch &Br) {
|
|
MachineInstr *MI = Br.MI;
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
if (!isThumb1)
|
|
llvm_unreachable("FixUpUnconditionalBr is Thumb1 only!");
|
|
|
|
// Use BL to implement far jump.
|
|
Br.MaxDisp = (1 << 21) * 2;
|
|
MI->setDesc(TII->get(ARM::tBfar));
|
|
BBSizes[MBB->getNumber()] += 2;
|
|
AdjustBBOffsetsAfter(MBB, 2);
|
|
HasFarJump = true;
|
|
NumUBrFixed++;
|
|
|
|
DEBUG(errs() << " Changed B to long jump " << *MI);
|
|
|
|
return true;
|
|
}
|
|
|
|
/// FixUpConditionalBr - Fix up a conditional branch whose destination is too
|
|
/// far away to fit in its displacement field. It is converted to an inverse
|
|
/// conditional branch + an unconditional branch to the destination.
|
|
bool
|
|
ARMConstantIslands::FixUpConditionalBr(MachineFunction &MF, ImmBranch &Br) {
|
|
MachineInstr *MI = Br.MI;
|
|
MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
|
|
|
|
// Add an unconditional branch to the destination and invert the branch
|
|
// condition to jump over it:
|
|
// blt L1
|
|
// =>
|
|
// bge L2
|
|
// b L1
|
|
// L2:
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
|
|
CC = ARMCC::getOppositeCondition(CC);
|
|
unsigned CCReg = MI->getOperand(2).getReg();
|
|
|
|
// If the branch is at the end of its MBB and that has a fall-through block,
|
|
// direct the updated conditional branch to the fall-through block. Otherwise,
|
|
// split the MBB before the next instruction.
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
MachineInstr *BMI = &MBB->back();
|
|
bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
|
|
|
|
NumCBrFixed++;
|
|
if (BMI != MI) {
|
|
if (llvm::next(MachineBasicBlock::iterator(MI)) == prior(MBB->end()) &&
|
|
BMI->getOpcode() == Br.UncondBr) {
|
|
// Last MI in the BB is an unconditional branch. Can we simply invert the
|
|
// condition and swap destinations:
|
|
// beq L1
|
|
// b L2
|
|
// =>
|
|
// bne L2
|
|
// b L1
|
|
MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
|
|
if (BBIsInRange(MI, NewDest, Br.MaxDisp)) {
|
|
DEBUG(errs() << " Invert Bcc condition and swap its destination with "
|
|
<< *BMI);
|
|
BMI->getOperand(0).setMBB(DestBB);
|
|
MI->getOperand(0).setMBB(NewDest);
|
|
MI->getOperand(1).setImm(CC);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (NeedSplit) {
|
|
SplitBlockBeforeInstr(MI);
|
|
// No need for the branch to the next block. We're adding an unconditional
|
|
// branch to the destination.
|
|
int delta = TII->GetInstSizeInBytes(&MBB->back());
|
|
BBSizes[MBB->getNumber()] -= delta;
|
|
MachineBasicBlock* SplitBB = llvm::next(MachineFunction::iterator(MBB));
|
|
AdjustBBOffsetsAfter(SplitBB, -delta);
|
|
MBB->back().eraseFromParent();
|
|
// BBOffsets[SplitBB] is wrong temporarily, fixed below
|
|
}
|
|
MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB));
|
|
|
|
DEBUG(errs() << " Insert B to BB#" << DestBB->getNumber()
|
|
<< " also invert condition and change dest. to BB#"
|
|
<< NextBB->getNumber() << "\n");
|
|
|
|
// Insert a new conditional branch and a new unconditional branch.
|
|
// Also update the ImmBranch as well as adding a new entry for the new branch.
|
|
BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
|
|
.addMBB(NextBB).addImm(CC).addReg(CCReg);
|
|
Br.MI = &MBB->back();
|
|
BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
|
|
BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
|
|
BBSizes[MBB->getNumber()] += TII->GetInstSizeInBytes(&MBB->back());
|
|
unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
|
|
ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
|
|
|
|
// Remove the old conditional branch. It may or may not still be in MBB.
|
|
BBSizes[MI->getParent()->getNumber()] -= TII->GetInstSizeInBytes(MI);
|
|
MI->eraseFromParent();
|
|
|
|
// The net size change is an addition of one unconditional branch.
|
|
int delta = TII->GetInstSizeInBytes(&MBB->back());
|
|
AdjustBBOffsetsAfter(MBB, delta);
|
|
return true;
|
|
}
|
|
|
|
/// UndoLRSpillRestore - Remove Thumb push / pop instructions that only spills
|
|
/// LR / restores LR to pc. FIXME: This is done here because it's only possible
|
|
/// to do this if tBfar is not used.
|
|
bool ARMConstantIslands::UndoLRSpillRestore() {
|
|
bool MadeChange = false;
|
|
for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
|
|
MachineInstr *MI = PushPopMIs[i];
|
|
// First two operands are predicates.
|
|
if (MI->getOpcode() == ARM::tPOP_RET &&
|
|
MI->getOperand(2).getReg() == ARM::PC &&
|
|
MI->getNumExplicitOperands() == 3) {
|
|
BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
|
|
MI->eraseFromParent();
|
|
MadeChange = true;
|
|
}
|
|
}
|
|
return MadeChange;
|
|
}
|
|
|
|
bool ARMConstantIslands::OptimizeThumb2Instructions(MachineFunction &MF) {
|
|
bool MadeChange = false;
|
|
|
|
// Shrink ADR and LDR from constantpool.
|
|
for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
|
|
CPUser &U = CPUsers[i];
|
|
unsigned Opcode = U.MI->getOpcode();
|
|
unsigned NewOpc = 0;
|
|
unsigned Scale = 1;
|
|
unsigned Bits = 0;
|
|
switch (Opcode) {
|
|
default: break;
|
|
case ARM::t2LEApcrel:
|
|
if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
|
|
NewOpc = ARM::tLEApcrel;
|
|
Bits = 8;
|
|
Scale = 4;
|
|
}
|
|
break;
|
|
case ARM::t2LDRpci:
|
|
if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
|
|
NewOpc = ARM::tLDRpci;
|
|
Bits = 8;
|
|
Scale = 4;
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (!NewOpc)
|
|
continue;
|
|
|
|
unsigned UserOffset = GetOffsetOf(U.MI) + 4;
|
|
unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
|
|
// FIXME: Check if offset is multiple of scale if scale is not 4.
|
|
if (CPEIsInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
|
|
U.MI->setDesc(TII->get(NewOpc));
|
|
MachineBasicBlock *MBB = U.MI->getParent();
|
|
BBSizes[MBB->getNumber()] -= 2;
|
|
AdjustBBOffsetsAfter(MBB, -2);
|
|
++NumT2CPShrunk;
|
|
MadeChange = true;
|
|
}
|
|
}
|
|
|
|
MadeChange |= OptimizeThumb2Branches(MF);
|
|
MadeChange |= OptimizeThumb2JumpTables(MF);
|
|
return MadeChange;
|
|
}
|
|
|
|
bool ARMConstantIslands::OptimizeThumb2Branches(MachineFunction &MF) {
|
|
bool MadeChange = false;
|
|
|
|
for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) {
|
|
ImmBranch &Br = ImmBranches[i];
|
|
unsigned Opcode = Br.MI->getOpcode();
|
|
unsigned NewOpc = 0;
|
|
unsigned Scale = 1;
|
|
unsigned Bits = 0;
|
|
switch (Opcode) {
|
|
default: break;
|
|
case ARM::t2B:
|
|
NewOpc = ARM::tB;
|
|
Bits = 11;
|
|
Scale = 2;
|
|
break;
|
|
case ARM::t2Bcc: {
|
|
NewOpc = ARM::tBcc;
|
|
Bits = 8;
|
|
Scale = 2;
|
|
break;
|
|
}
|
|
}
|
|
if (NewOpc) {
|
|
unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
|
|
MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
|
|
if (BBIsInRange(Br.MI, DestBB, MaxOffs)) {
|
|
Br.MI->setDesc(TII->get(NewOpc));
|
|
MachineBasicBlock *MBB = Br.MI->getParent();
|
|
BBSizes[MBB->getNumber()] -= 2;
|
|
AdjustBBOffsetsAfter(MBB, -2);
|
|
++NumT2BrShrunk;
|
|
MadeChange = true;
|
|
}
|
|
}
|
|
|
|
Opcode = Br.MI->getOpcode();
|
|
if (Opcode != ARM::tBcc)
|
|
continue;
|
|
|
|
NewOpc = 0;
|
|
unsigned PredReg = 0;
|
|
ARMCC::CondCodes Pred = llvm::getInstrPredicate(Br.MI, PredReg);
|
|
if (Pred == ARMCC::EQ)
|
|
NewOpc = ARM::tCBZ;
|
|
else if (Pred == ARMCC::NE)
|
|
NewOpc = ARM::tCBNZ;
|
|
if (!NewOpc)
|
|
continue;
|
|
MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
|
|
// Check if the distance is within 126. Subtract starting offset by 2
|
|
// because the cmp will be eliminated.
|
|
unsigned BrOffset = GetOffsetOf(Br.MI) + 4 - 2;
|
|
unsigned DestOffset = BBOffsets[DestBB->getNumber()];
|
|
if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) {
|
|
MachineBasicBlock::iterator CmpMI = Br.MI; --CmpMI;
|
|
if (CmpMI->getOpcode() == ARM::tCMPzi8) {
|
|
unsigned Reg = CmpMI->getOperand(0).getReg();
|
|
Pred = llvm::getInstrPredicate(CmpMI, PredReg);
|
|
if (Pred == ARMCC::AL &&
|
|
CmpMI->getOperand(1).getImm() == 0 &&
|
|
isARMLowRegister(Reg)) {
|
|
MachineBasicBlock *MBB = Br.MI->getParent();
|
|
MachineInstr *NewBR =
|
|
BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
|
|
.addReg(Reg).addMBB(DestBB, Br.MI->getOperand(0).getTargetFlags());
|
|
CmpMI->eraseFromParent();
|
|
Br.MI->eraseFromParent();
|
|
Br.MI = NewBR;
|
|
BBSizes[MBB->getNumber()] -= 2;
|
|
AdjustBBOffsetsAfter(MBB, -2);
|
|
++NumCBZ;
|
|
MadeChange = true;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return MadeChange;
|
|
}
|
|
|
|
/// OptimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
|
|
/// jumptables when it's possible.
|
|
bool ARMConstantIslands::OptimizeThumb2JumpTables(MachineFunction &MF) {
|
|
bool MadeChange = false;
|
|
|
|
// FIXME: After the tables are shrunk, can we get rid some of the
|
|
// constantpool tables?
|
|
MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
|
|
if (MJTI == 0) return false;
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
|
|
MachineInstr *MI = T2JumpTables[i];
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
unsigned NumOps = TID.getNumOperands();
|
|
unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2);
|
|
MachineOperand JTOP = MI->getOperand(JTOpIdx);
|
|
unsigned JTI = JTOP.getIndex();
|
|
assert(JTI < JT.size());
|
|
|
|
bool ByteOk = true;
|
|
bool HalfWordOk = true;
|
|
unsigned JTOffset = GetOffsetOf(MI) + 4;
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
|
for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
|
|
MachineBasicBlock *MBB = JTBBs[j];
|
|
unsigned DstOffset = BBOffsets[MBB->getNumber()];
|
|
// Negative offset is not ok. FIXME: We should change BB layout to make
|
|
// sure all the branches are forward.
|
|
if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
|
|
ByteOk = false;
|
|
unsigned TBHLimit = ((1<<16)-1)*2;
|
|
if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
|
|
HalfWordOk = false;
|
|
if (!ByteOk && !HalfWordOk)
|
|
break;
|
|
}
|
|
|
|
if (ByteOk || HalfWordOk) {
|
|
MachineBasicBlock *MBB = MI->getParent();
|
|
unsigned BaseReg = MI->getOperand(0).getReg();
|
|
bool BaseRegKill = MI->getOperand(0).isKill();
|
|
if (!BaseRegKill)
|
|
continue;
|
|
unsigned IdxReg = MI->getOperand(1).getReg();
|
|
bool IdxRegKill = MI->getOperand(1).isKill();
|
|
MachineBasicBlock::iterator PrevI = MI;
|
|
if (PrevI == MBB->begin())
|
|
continue;
|
|
|
|
MachineInstr *AddrMI = --PrevI;
|
|
bool OptOk = true;
|
|
// Examine the instruction that calculate the jumptable entry address.
|
|
// If it's not the one just before the t2BR_JT, we won't delete it, then
|
|
// it's not worth doing the optimization.
|
|
for (unsigned k = 0, eee = AddrMI->getNumOperands(); k != eee; ++k) {
|
|
const MachineOperand &MO = AddrMI->getOperand(k);
|
|
if (!MO.isReg() || !MO.getReg())
|
|
continue;
|
|
if (MO.isDef() && MO.getReg() != BaseReg) {
|
|
OptOk = false;
|
|
break;
|
|
}
|
|
if (MO.isUse() && !MO.isKill() && MO.getReg() != IdxReg) {
|
|
OptOk = false;
|
|
break;
|
|
}
|
|
}
|
|
if (!OptOk)
|
|
continue;
|
|
|
|
// The previous instruction should be a tLEApcrel or t2LEApcrelJT, we want
|
|
// to delete it as well.
|
|
MachineInstr *LeaMI = --PrevI;
|
|
if ((LeaMI->getOpcode() != ARM::tLEApcrelJT &&
|
|
LeaMI->getOpcode() != ARM::t2LEApcrelJT) ||
|
|
LeaMI->getOperand(0).getReg() != BaseReg)
|
|
OptOk = false;
|
|
|
|
if (!OptOk)
|
|
continue;
|
|
|
|
unsigned Opc = ByteOk ? ARM::t2TBB : ARM::t2TBH;
|
|
MachineInstr *NewJTMI = BuildMI(MBB, MI->getDebugLoc(), TII->get(Opc))
|
|
.addReg(IdxReg, getKillRegState(IdxRegKill))
|
|
.addJumpTableIndex(JTI, JTOP.getTargetFlags())
|
|
.addImm(MI->getOperand(JTOpIdx+1).getImm());
|
|
// FIXME: Insert an "ALIGN" instruction to ensure the next instruction
|
|
// is 2-byte aligned. For now, asm printer will fix it up.
|
|
unsigned NewSize = TII->GetInstSizeInBytes(NewJTMI);
|
|
unsigned OrigSize = TII->GetInstSizeInBytes(AddrMI);
|
|
OrigSize += TII->GetInstSizeInBytes(LeaMI);
|
|
OrigSize += TII->GetInstSizeInBytes(MI);
|
|
|
|
AddrMI->eraseFromParent();
|
|
LeaMI->eraseFromParent();
|
|
MI->eraseFromParent();
|
|
|
|
int delta = OrigSize - NewSize;
|
|
BBSizes[MBB->getNumber()] -= delta;
|
|
AdjustBBOffsetsAfter(MBB, -delta);
|
|
|
|
++NumTBs;
|
|
MadeChange = true;
|
|
}
|
|
}
|
|
|
|
return MadeChange;
|
|
}
|
|
|
|
/// ReorderThumb2JumpTables - Adjust the function's block layout to ensure that
|
|
/// jump tables always branch forwards, since that's what tbb and tbh need.
|
|
bool ARMConstantIslands::ReorderThumb2JumpTables(MachineFunction &MF) {
|
|
bool MadeChange = false;
|
|
|
|
MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
|
|
if (MJTI == 0) return false;
|
|
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
|
|
MachineInstr *MI = T2JumpTables[i];
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
unsigned NumOps = TID.getNumOperands();
|
|
unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2);
|
|
MachineOperand JTOP = MI->getOperand(JTOpIdx);
|
|
unsigned JTI = JTOP.getIndex();
|
|
assert(JTI < JT.size());
|
|
|
|
// We prefer if target blocks for the jump table come after the jump
|
|
// instruction so we can use TB[BH]. Loop through the target blocks
|
|
// and try to adjust them such that that's true.
|
|
int JTNumber = MI->getParent()->getNumber();
|
|
const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
|
|
for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
|
|
MachineBasicBlock *MBB = JTBBs[j];
|
|
int DTNumber = MBB->getNumber();
|
|
|
|
if (DTNumber < JTNumber) {
|
|
// The destination precedes the switch. Try to move the block forward
|
|
// so we have a positive offset.
|
|
MachineBasicBlock *NewBB =
|
|
AdjustJTTargetBlockForward(MBB, MI->getParent());
|
|
if (NewBB)
|
|
MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
|
|
MadeChange = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
return MadeChange;
|
|
}
|
|
|
|
MachineBasicBlock *ARMConstantIslands::
|
|
AdjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB)
|
|
{
|
|
MachineFunction &MF = *BB->getParent();
|
|
|
|
// If it's the destination block is terminated by an unconditional branch,
|
|
// try to move it; otherwise, create a new block following the jump
|
|
// table that branches back to the actual target. This is a very simple
|
|
// heuristic. FIXME: We can definitely improve it.
|
|
MachineBasicBlock *TBB = 0, *FBB = 0;
|
|
SmallVector<MachineOperand, 4> Cond;
|
|
SmallVector<MachineOperand, 4> CondPrior;
|
|
MachineFunction::iterator BBi = BB;
|
|
MachineFunction::iterator OldPrior = prior(BBi);
|
|
|
|
// If the block terminator isn't analyzable, don't try to move the block
|
|
bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond);
|
|
|
|
// If the block ends in an unconditional branch, move it. The prior block
|
|
// has to have an analyzable terminator for us to move this one. Be paranoid
|
|
// and make sure we're not trying to move the entry block of the function.
|
|
if (!B && Cond.empty() && BB != MF.begin() &&
|
|
!TII->AnalyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
|
|
BB->moveAfter(JTBB);
|
|
OldPrior->updateTerminator();
|
|
BB->updateTerminator();
|
|
// Update numbering to account for the block being moved.
|
|
MF.RenumberBlocks();
|
|
++NumJTMoved;
|
|
return NULL;
|
|
}
|
|
|
|
// Create a new MBB for the code after the jump BB.
|
|
MachineBasicBlock *NewBB =
|
|
MF.CreateMachineBasicBlock(JTBB->getBasicBlock());
|
|
MachineFunction::iterator MBBI = JTBB; ++MBBI;
|
|
MF.insert(MBBI, NewBB);
|
|
|
|
// Add an unconditional branch from NewBB to BB.
|
|
// There doesn't seem to be meaningful DebugInfo available; this doesn't
|
|
// correspond directly to anything in the source.
|
|
assert (isThumb2 && "Adjusting for TB[BH] but not in Thumb2?");
|
|
BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B)).addMBB(BB);
|
|
|
|
// Update internal data structures to account for the newly inserted MBB.
|
|
MF.RenumberBlocks(NewBB);
|
|
|
|
// Update the CFG.
|
|
NewBB->addSuccessor(BB);
|
|
JTBB->removeSuccessor(BB);
|
|
JTBB->addSuccessor(NewBB);
|
|
|
|
++NumJTInserted;
|
|
return NewBB;
|
|
}
|