llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 05:29:23 +00:00

History

Tim Northover 0eb313be18 ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts

The previous patterns directly inserted FMOV or INS instructions into
the DAG for scalar_to_vector & bitconvert patterns. This is horribly
inefficient and can generated lots more GPR <-> FPR register traffic
than necessary.

It's much better to emit instructions the register allocator
understands so it can coalesce the copies when appropriate.

It led to at least one ISelLowering hack to avoid the problems, which
was incorrect for v1i64 (FPR64 has no dsub). It can now be removed
entirely.

This should also fix PR19331.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205616 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-04 09:03:09 +00:00

AArch64

[AArch64] Lower SHL_PARTS, SRA_PARTS and SRL_PARTS

2014-03-27 16:28:09 +00:00

ARM

ARM: yet another round of ARM test clean ups

2014-04-03 23:47:24 +00:00

ARM64

ARM64: use regalloc-friendly COPY_TO_REGCLASS for bitcasts

2014-04-04 09:03:09 +00:00

CPP

Begin adding docs and IR-level support for the inalloca attribute