llvm-6502/test/CodeGen
Benjamin Kramer 17347912b4 X86: Emit vector sext as shuffle + sra if vpmovsx is not available.
Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better
than scalarized loads. Fixes PR14590.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22 11:34:28 +00:00
..
ARM Revert "Adding support for llvm.arm.neon.vaddl[su].* and" 2012-12-20 21:09:38 +00:00
CPP
Generic After reducing the size of an operation in the DAG we zero-extend the reduced 2012-12-19 07:39:08 +00:00
Hexagon
MBlaze
Mips Add test case for r170674 2012-12-21 00:55:10 +00:00
MSP430
NVPTX
PowerPC Simplify the testcase a bit. 2012-12-20 17:47:27 +00:00
R600 R600: Expand vec4 INT <-> FP conversions 2012-12-21 16:33:24 +00:00
SI
SPARC
Thumb
Thumb2 On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, 2012-12-20 19:59:30 +00:00
X86 X86: Emit vector sext as shuffle + sra if vpmovsx is not available. 2012-12-22 11:34:28 +00:00
XCore