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https://github.com/c64scene-ar/llvm-6502.git
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7ca2a7d742
Adds code generation support for dcbtst (data cache prefetch for write) and icbt (instruction cache prefetch for read - Book E cores only). We still end up with a 'cannot select' error for the non-supported prefetch intrinsic forms. This will be fixed in a later commit. Fixes PR20692. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216339 91177308-0d34-0410-b5e6-96231b3b80d8
81 lines
1.6 KiB
Plaintext
81 lines
1.6 KiB
Plaintext
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr7 | FileCheck %s
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# CHECK: icbi 2, 3
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0x7c 0x02 0x1f 0xac
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# CHECK: icbt 0, 5, 31
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0x7c 0x05 0xf8 0x2c
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# CHECK: dcbt 2, 3
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0x7c 0x02 0x1a 0x2c
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# CHECK: dcbtst 2, 3
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0x7c 0x02 0x19 0xec
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# CHECK: dcbz 2, 3
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0x7c 0x02 0x1f 0xec
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# CHECK: dcbst 2, 3
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0x7c 0x02 0x18 0x6c
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# CHECK: isync
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0x4c 0x00 0x01 0x2c
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# CHECK: stwcx. 2, 3, 4
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0x7c 0x43 0x21 0x2d
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# CHECK: stdcx. 2, 3, 4
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0x7c 0x43 0x21 0xad
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# CHECK: sync 2
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0x7c 0x40 0x04 0xac
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# CHECK: eieio
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0x7c 0x00 0x06 0xac
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# CHECK: wait 2
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0x7c 0x40 0x00 0x7c
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# CHECK: mbar 1
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0x7c 0x20 0x06 0xac
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# CHECK: dcbf 2, 3
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0x7c 0x02 0x18 0xac
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# CHECK: lwarx 2, 3, 4
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0x7c 0x43 0x20 0x28
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# CHECK: ldarx 2, 3, 4
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0x7c 0x43 0x20 0xa8
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# CHECK: sync 0
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0x7c 0x00 0x04 0xac
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# CHECK: sync 0
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0x7c 0x00 0x04 0xac
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# CHECK: sync 1
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0x7c 0x20 0x04 0xac
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# CHECK: sync 2
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0x7c 0x40 0x04 0xac
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# CHECK: wait 0
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0x7c 0x00 0x00 0x7c
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# CHECK: wait 1
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0x7c 0x20 0x00 0x7c
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# CHECK: wait 2
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0x7c 0x40 0x00 0x7c
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# CHECK: mftb 2, 123
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0x7c 0x5b 0x1a 0xe6
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# CHECK: mftb 2, 268
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0x7c 0x4c 0x42 0xe6
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# CHECK: mftb 2, 269
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0x7c 0x4d 0x42 0xe6
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