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llvm-6502/lib/Target/R600
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Benjamin Kramer 1983a4cbf1 R600: Don't compare iterators of different maps. 
Found be libstdc's debug mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-07 19:59:34 +00:00
..
InstPrinter
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MCTargetDesc
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TargetInfo
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AMDGPU.h
R600: Add a pass that merge Vector Register
2013-06-05 21:38:04 +00:00
AMDGPU.td
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AMDGPUAsmPrinter.cpp
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AMDGPUAsmPrinter.h
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AMDGPUCallingConv.td
R600/SI: Add a calling convention for compute shaders
2013-06-03 17:40:11 +00:00
AMDGPUConvertToISA.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUIndirectAddressing.cpp
R600: Don't compare iterators of different maps.
2013-06-07 19:59:34 +00:00
AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td
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AMDGPUInstructions.td
R600/SI: Add support for global loads
2013-06-03 17:39:43 +00:00
AMDGPUIntrinsics.td
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AMDGPUISelLowering.cpp
R600/SI: Add a calling convention for compute shaders
2013-06-03 17:40:11 +00:00
AMDGPUISelLowering.h
R600/SI: Add support for work item and work group intrinsics
2013-06-03 17:40:18 +00:00
AMDGPUMachineFunction.cpp
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AMDGPUMachineFunction.h
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AMDGPUMCInstLower.cpp
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AMDGPUMCInstLower.h
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AMDGPURegisterInfo.cpp
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AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPUStructurizeCFG.cpp
Silencing an MSVC warning about mixing bool and unsigned int.
2013-06-04 01:03:03 +00:00
AMDGPUSubtarget.cpp
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AMDGPUSubtarget.h
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AMDGPUTargetMachine.cpp
R600: Add a pass that merge Vector Register
2013-06-05 21:38:04 +00:00
AMDGPUTargetMachine.h
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AMDIL7XXDevice.cpp
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AMDIL7XXDevice.h
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AMDIL.h
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AMDILBase.td
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AMDILCFGStructurizer.cpp
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AMDILDevice.cpp
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AMDILDevice.h
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AMDILDeviceInfo.cpp
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AMDILDeviceInfo.h
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AMDILDevices.h
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AMDILEvergreenDevice.cpp
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AMDILEvergreenDevice.h
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AMDILInstrInfo.td
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AMDILIntrinsicInfo.cpp
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AMDILIntrinsicInfo.h
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AMDILIntrinsics.td
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AMDILISelDAGToDAG.cpp
Cast to the proper type.
2013-06-06 01:04:21 +00:00
AMDILISelLowering.cpp
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AMDILNIDevice.cpp
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AMDILNIDevice.h
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AMDILRegisterInfo.td
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AMDILSIDevice.cpp
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AMDILSIDevice.h
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CMakeLists.txt
R600: Add a pass that merge Vector Register
2013-06-05 21:38:04 +00:00
LLVMBuild.txt
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Makefile
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Processors.td
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R600ControlFlowFinalizer.cpp
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R600Defines.h
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R600EmitClauseMarkers.cpp
R600: Const/Neg/Abs can be folded to dot4
2013-06-04 23:17:15 +00:00
R600ExpandSpecialInstrs.cpp
R600: Const/Neg/Abs can be folded to dot4
2013-06-04 23:17:15 +00:00
R600InstrInfo.cpp
R600: Make sure to schedule AR register uses and defs in the same clause
2013-06-05 03:43:06 +00:00
R600InstrInfo.h
R600: Const/Neg/Abs can be folded to dot4
2013-06-04 23:17:15 +00:00
R600Instructions.td
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R600Intrinsics.td
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R600ISelLowering.cpp
R600: Swizzle texture/export instructions
2013-06-04 15:04:53 +00:00
R600ISelLowering.h
R600: Swizzle texture/export instructions
2013-06-04 15:04:53 +00:00
R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
R600: Remove leftover code in R600MachineScheduler.cpp
2013-06-06 14:18:29 +00:00
R600MachineScheduler.h
R600: Schedule copy from phys register at beginning of block
2013-06-05 20:27:35 +00:00
R600OptimizeVectorRegisters.cpp
Vincent says the element is at most once in the vector, so we don't need a full std::remove.
2013-06-07 18:18:12 +00:00
R600Packetizer.cpp
R600: 3 op instructions have no write bit but the result are store in PV
2013-06-03 15:56:12 +00:00
R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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SIAnnotateControlFlow.cpp
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SIDefines.h
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SIInsertWaits.cpp
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SIInstrFormats.td
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SIInstrInfo.cpp
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SIInstrInfo.h
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SIInstrInfo.td
Cast to the correct type. Pointer, not reference.
2013-06-06 05:39:29 +00:00
SIInstructions.td
R600/SI: Add support for global loads
2013-06-03 17:39:43 +00:00
SIIntrinsics.td
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SIISelLowering.cpp
R600: Replace predicate loop with predicate function
2013-06-05 23:39:50 +00:00
SIISelLowering.h
R600/SI: Add support for work item and work group intrinsics
2013-06-03 17:40:18 +00:00
SILowerControlFlow.cpp
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SIMachineFunctionInfo.cpp
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SIMachineFunctionInfo.h
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SIRegisterInfo.cpp
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SIRegisterInfo.h
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SIRegisterInfo.td
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SISchedule.td
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