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c7e1888d93
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173221 91177308-0d34-0410-b5e6-96231b3b80d8
146 lines
4.7 KiB
C++
146 lines
4.7 KiB
C++
//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition of the TargetLowering class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPUISELLOWERING_H
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#define AMDGPUISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class MachineRegisterInfo;
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class AMDGPUTargetLowering : public TargetLowering {
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private:
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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protected:
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/// \brief Helper function that adds Reg to the LiveIn list of the DAG's
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg.
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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bool isHWTrueValue(SDValue Op) const;
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bool isHWFalseValue(SDValue Op) const;
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public:
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AMDGPUTargetLowering(TargetMachine &TM);
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virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc DL, SelectionDAG &DAG) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
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virtual const char* getTargetNodeName(unsigned Opcode) const;
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// Functions defined in AMDILISelLowering.cpp
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public:
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/// \brief Determine which of the bits specified in \p Mask are known to be
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/// either zero or one and return them in the \p KnownZero and \p KnownOne
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/// bitsets.
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virtual void computeMaskedBitsForTargetNode(const SDValue Op,
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APInt &KnownZero,
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APInt &KnownOne,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
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const CallInst &I, unsigned Intrinsic) const;
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/// We want to mark f32/f64 floating point values as legal.
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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/// We don't want to shrink f64/f32 constants.
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bool ShouldShrinkFPConstant(EVT VT) const;
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private:
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void InitAMDILLowering();
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SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
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};
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namespace AMDGPUISD {
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enum {
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// AMDIL ISD Opcodes
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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MAD, // 32bit Fused Multiply Add instruction
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CALL, // Function call based on a single integer
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UMUL, // 32bit unsigned multiplication
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DIV_INF, // Divide with infinity returned on zero divisor
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RET_FLAG,
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BRANCH_COND,
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// End AMDIL ISD Opcodes
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BITALIGN,
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DWORDADDR,
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FRACT,
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FMAX,
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SMAX,
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UMAX,
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FMIN,
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SMIN,
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UMIN,
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URECIP,
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INTERP,
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INTERP_P0,
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EXPORT,
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CONST_ADDRESS,
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LAST_AMDGPU_ISD_NUMBER
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};
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} // End namespace AMDGPUISD
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namespace SIISD {
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enum {
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SI_FIRST = AMDGPUISD::LAST_AMDGPU_ISD_NUMBER,
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VCC_AND,
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VCC_BITCAST
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};
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} // End namespace SIISD
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} // End namespace llvm
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#endif // AMDGPUISELLOWERING_H
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