Scott Michel 1a6cdb6b50 CellSPU: ... - Fix v2[if]64 vector insertion code before IBM files a bug report. - Ensure that zero (0) offsets relative to $sp don't trip an assert (add $sp, 0 gets legalized to $sp alone, tripping an assert) - Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60358 91177308-0d34-0410-b5e6-96231b3b80d8		2008-12-01 17:56:02 +00:00
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Alpha
ARM
CBackend
CellSPU	CellSPU:	2008-12-01 17:56:02 +00:00
CPP
Generic
IA64
Mips
PowerPC	Check that running the DAG combiner between type	2008-11-26 16:44:30 +00:00
SPARC
X86	Followup to r60283: optimize arbitrary width signed divisions as well	2008-11-30 06:35:39 +00:00
XCore