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a2fd5b5fd0
Completely empty subranges are not allowed and must be removed when subreg liveness is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224804 91177308-0d34-0410-b5e6-96231b3b80d8
428 lines
14 KiB
C++
428 lines
14 KiB
C++
//===-- LiveRangeEdit.cpp - Basic tools for editing a register live range -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveRangeEdit.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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STATISTIC(NumDCEDeleted, "Number of instructions deleted by DCE");
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STATISTIC(NumDCEFoldedLoads, "Number of single use loads folded after DCE");
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STATISTIC(NumFracRanges, "Number of live ranges fractured by DCE");
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void LiveRangeEdit::Delegate::anchor() { }
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LiveInterval &LiveRangeEdit::createEmptyIntervalFrom(unsigned OldReg) {
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unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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if (VRM) {
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VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
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}
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LiveInterval &LI = LIS.createEmptyInterval(VReg);
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return LI;
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}
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unsigned LiveRangeEdit::createFrom(unsigned OldReg) {
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unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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if (VRM) {
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VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
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}
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return VReg;
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}
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bool LiveRangeEdit::checkRematerializable(VNInfo *VNI,
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const MachineInstr *DefMI,
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AliasAnalysis *aa) {
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assert(DefMI && "Missing instruction");
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ScannedRemattable = true;
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if (!TII.isTriviallyReMaterializable(DefMI, aa))
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return false;
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Remattable.insert(VNI);
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return true;
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}
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void LiveRangeEdit::scanRemattable(AliasAnalysis *aa) {
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for (VNInfo *VNI : getParent().valnos) {
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if (VNI->isUnused())
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continue;
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MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
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if (!DefMI)
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continue;
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checkRematerializable(VNI, DefMI, aa);
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}
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ScannedRemattable = true;
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}
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bool LiveRangeEdit::anyRematerializable(AliasAnalysis *aa) {
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if (!ScannedRemattable)
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scanRemattable(aa);
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return !Remattable.empty();
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}
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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SlotIndex OrigIdx,
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SlotIndex UseIdx) const {
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OrigIdx = OrigIdx.getRegSlot(true);
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UseIdx = UseIdx.getRegSlot(true);
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for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = OrigMI->getOperand(i);
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if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
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continue;
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// We can't remat physreg uses, unless it is a constant.
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if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
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if (MRI.isConstantPhysReg(MO.getReg(), *OrigMI->getParent()->getParent()))
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continue;
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return false;
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}
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LiveInterval &li = LIS.getInterval(MO.getReg());
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const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
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if (!OVNI)
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continue;
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// Don't allow rematerialization immediately after the original def.
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// It would be incorrect if OrigMI redefines the register.
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// See PR14098.
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if (SlotIndex::isSameInstr(OrigIdx, UseIdx))
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return false;
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if (OVNI != li.getVNInfoAt(UseIdx))
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return false;
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}
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return true;
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}
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bool LiveRangeEdit::canRematerializeAt(Remat &RM,
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SlotIndex UseIdx,
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bool cheapAsAMove) {
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assert(ScannedRemattable && "Call anyRematerializable first");
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// Use scanRemattable info.
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if (!Remattable.count(RM.ParentVNI))
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return false;
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// No defining instruction provided.
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SlotIndex DefIdx;
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if (RM.OrigMI)
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DefIdx = LIS.getInstructionIndex(RM.OrigMI);
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else {
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DefIdx = RM.ParentVNI->def;
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RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
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assert(RM.OrigMI && "No defining instruction for remattable value");
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}
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// If only cheap remats were requested, bail out early.
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if (cheapAsAMove && !TII.isAsCheapAsAMove(RM.OrigMI))
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return false;
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// Verify that all used registers are available with the same values.
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if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
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return false;
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return true;
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}
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SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const Remat &RM,
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const TargetRegisterInfo &tri,
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bool Late) {
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assert(RM.OrigMI && "Invalid remat");
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TII.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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Rematted.insert(RM.ParentVNI);
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return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
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.getRegSlot();
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}
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void LiveRangeEdit::eraseVirtReg(unsigned Reg) {
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if (TheDelegate && TheDelegate->LRE_CanEraseVirtReg(Reg))
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LIS.removeInterval(Reg);
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}
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bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
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SmallVectorImpl<MachineInstr*> &Dead) {
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MachineInstr *DefMI = nullptr, *UseMI = nullptr;
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// Check that there is a single def and a single use.
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for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
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MachineInstr *MI = MO.getParent();
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if (MO.isDef()) {
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if (DefMI && DefMI != MI)
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return false;
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if (!MI->canFoldAsLoad())
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return false;
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DefMI = MI;
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} else if (!MO.isUndef()) {
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if (UseMI && UseMI != MI)
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return false;
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// FIXME: Targets don't know how to fold subreg uses.
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if (MO.getSubReg())
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return false;
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UseMI = MI;
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}
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}
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if (!DefMI || !UseMI)
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return false;
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// Since we're moving the DefMI load, make sure we're not extending any live
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// ranges.
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if (!allUsesAvailableAt(DefMI,
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LIS.getInstructionIndex(DefMI),
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LIS.getInstructionIndex(UseMI)))
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return false;
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// We also need to make sure it is safe to move the load.
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// Assume there are stores between DefMI and UseMI.
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bool SawStore = true;
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if (!DefMI->isSafeToMove(&TII, nullptr, SawStore))
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return false;
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DEBUG(dbgs() << "Try to fold single def: " << *DefMI
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<< " into single use: " << *UseMI);
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SmallVector<unsigned, 8> Ops;
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if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
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return false;
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MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
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if (!FoldMI)
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return false;
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DEBUG(dbgs() << " folded: " << *FoldMI);
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LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
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UseMI->eraseFromParent();
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DefMI->addRegisterDead(LI->reg, nullptr);
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Dead.push_back(DefMI);
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++NumDCEFoldedLoads;
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return true;
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}
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/// Find all live intervals that need to shrink, then remove the instruction.
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void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
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assert(MI->allDefsAreDead() && "Def isn't really dead");
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SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
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// Never delete a bundled instruction.
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if (MI->isBundled()) {
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return;
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}
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// Never delete inline asm.
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if (MI->isInlineAsm()) {
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DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
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return;
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}
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// Use the same criteria as DeadMachineInstructionElim.
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bool SawStore = false;
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if (!MI->isSafeToMove(&TII, nullptr, SawStore)) {
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DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
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return;
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}
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DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
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// Collect virtual registers to be erased after MI is gone.
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SmallVector<unsigned, 8> RegsToErase;
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bool ReadsPhysRegs = false;
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// Check for live intervals that may shrink
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for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
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MOE = MI->operands_end(); MOI != MOE; ++MOI) {
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if (!MOI->isReg())
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continue;
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unsigned Reg = MOI->getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
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// Check if MI reads any unreserved physregs.
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if (Reg && MOI->readsReg() && !MRI.isReserved(Reg))
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ReadsPhysRegs = true;
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else if (MOI->isDef()) {
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for (MCRegUnitIterator Units(Reg, MRI.getTargetRegisterInfo());
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Units.isValid(); ++Units) {
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if (LiveRange *LR = LIS.getCachedRegUnit(*Units)) {
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if (VNInfo *VNI = LR->getVNInfoAt(Idx))
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LR->removeValNo(VNI);
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}
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}
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}
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continue;
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}
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LiveInterval &LI = LIS.getInterval(Reg);
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// Shrink read registers, unless it is likely to be expensive and
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// unlikely to change anything. We typically don't want to shrink the
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// PIC base register that has lots of uses everywhere.
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// Always shrink COPY uses that probably come from live range splitting.
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if (MI->readsVirtualRegister(Reg) &&
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(MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) ||
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LI.Query(Idx).isKill()))
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ToShrink.insert(&LI);
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// Remove defined value.
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if (MOI->isDef()) {
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if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
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if (TheDelegate)
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TheDelegate->LRE_WillShrinkVirtReg(LI.reg);
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LI.removeValNo(VNI);
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if (LI.empty()) {
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RegsToErase.push_back(Reg);
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} else {
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// Also remove the value in subranges.
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for (LiveInterval::SubRange &S : LI.subranges()) {
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if (VNInfo *SVNI = S.getVNInfoAt(Idx))
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S.removeValNo(SVNI);
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}
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LI.removeEmptySubRanges();
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}
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}
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}
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}
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// Currently, we don't support DCE of physreg live ranges. If MI reads
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// any unreserved physregs, don't erase the instruction, but turn it into
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// a KILL instead. This way, the physreg live ranges don't end up
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// dangling.
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// FIXME: It would be better to have something like shrinkToUses() for
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// physregs. That could potentially enable more DCE and it would free up
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// the physreg. It would not happen often, though.
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if (ReadsPhysRegs) {
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MI->setDesc(TII.get(TargetOpcode::KILL));
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// Remove all operands that aren't physregs.
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for (unsigned i = MI->getNumOperands(); i; --i) {
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const MachineOperand &MO = MI->getOperand(i-1);
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if (MO.isReg() && TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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continue;
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MI->RemoveOperand(i-1);
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}
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DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
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} else {
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if (TheDelegate)
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TheDelegate->LRE_WillEraseInstruction(MI);
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LIS.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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++NumDCEDeleted;
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}
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// Erase any virtregs that are now empty and unused. There may be <undef>
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// uses around. Keep the empty live range in that case.
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for (unsigned i = 0, e = RegsToErase.size(); i != e; ++i) {
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unsigned Reg = RegsToErase[i];
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if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) {
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ToShrink.remove(&LIS.getInterval(Reg));
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eraseVirtReg(Reg);
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}
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}
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}
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void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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ArrayRef<unsigned> RegsBeingSpilled) {
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ToShrinkSet ToShrink;
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for (;;) {
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// Erase all dead defs.
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while (!Dead.empty())
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eliminateDeadDef(Dead.pop_back_val(), ToShrink);
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if (ToShrink.empty())
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break;
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// Shrink just one live interval. Then delete new dead defs.
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LiveInterval *LI = ToShrink.back();
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ToShrink.pop_back();
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if (foldAsLoad(LI, Dead))
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continue;
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if (TheDelegate)
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TheDelegate->LRE_WillShrinkVirtReg(LI->reg);
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if (!LIS.shrinkToUses(LI, &Dead))
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continue;
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// Don't create new intervals for a register being spilled.
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// The new intervals would have to be spilled anyway so its not worth it.
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// Also they currently aren't spilled so creating them and not spilling
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// them results in incorrect code.
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bool BeingSpilled = false;
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for (unsigned i = 0, e = RegsBeingSpilled.size(); i != e; ++i) {
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if (LI->reg == RegsBeingSpilled[i]) {
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BeingSpilled = true;
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break;
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}
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}
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if (BeingSpilled) continue;
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// LI may have been separated, create new intervals.
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LI->RenumberValues();
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ConnectedVNInfoEqClasses ConEQ(LIS);
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unsigned NumComp = ConEQ.Classify(LI);
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if (NumComp <= 1)
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continue;
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++NumFracRanges;
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bool IsOriginal = VRM && VRM->getOriginal(LI->reg) == LI->reg;
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DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
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SmallVector<LiveInterval*, 8> Dups(1, LI);
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for (unsigned i = 1; i != NumComp; ++i) {
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Dups.push_back(&createEmptyIntervalFrom(LI->reg));
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// If LI is an original interval that hasn't been split yet, make the new
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// intervals their own originals instead of referring to LI. The original
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// interval must contain all the split products, and LI doesn't.
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if (IsOriginal)
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VRM->setIsSplitFromReg(Dups.back()->reg, 0);
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if (TheDelegate)
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TheDelegate->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
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}
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ConEQ.Distribute(&Dups[0], MRI);
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DEBUG({
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for (unsigned i = 0; i != NumComp; ++i)
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dbgs() << '\t' << *Dups[i] << '\n';
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});
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}
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}
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// Keep track of new virtual registers created via
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// MachineRegisterInfo::createVirtualRegister.
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void
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LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
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{
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if (VRM)
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VRM->grow();
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NewRegs.push_back(VReg);
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}
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void
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LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
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const MachineLoopInfo &Loops,
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const MachineBlockFrequencyInfo &MBFI) {
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VirtRegAuxInfo VRAI(MF, LIS, Loops, MBFI);
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for (unsigned I = 0, Size = size(); I < Size; ++I) {
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LiveInterval &LI = LIS.getInterval(get(I));
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if (MRI.recomputeRegClass(LI.reg, MF.getTarget()))
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DEBUG({
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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dbgs() << "Inflated " << PrintReg(LI.reg) << " to "
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<< TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';
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});
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VRAI.calculateSpillWeightAndHint(LI);
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}
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}
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