Tom Stellard 8c009e3943 R600: Re-enable sub-reg liveness ...

The bug in the R600 backend that this uncovered has been fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238999 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-04 01:20:04 +00:00

..

AsmParser

MC: Clean up MCExpr naming. NFC.

2015-05-30 01:25:56 +00:00

InstPrinter

R600/SI: Initial support for assembler and inline assembly

2015-04-08 01:09:26 +00:00

MCTargetDesc

Use std::bitset for SubtargetFeatures.

2015-05-26 10:47:10 +00:00

TargetInfo

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AMDGPU.h

R600/SI: add pass to mark CF live ranges as non-spillable

2015-05-12 17:13:02 +00:00

AMDGPU.td

R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips

2015-05-25 16:15:54 +00:00

AMDGPUAlwaysInlinePass.cpp

R600: Fix always inline pass breaking noinline functions

2015-04-22 17:10:44 +00:00

AMDGPUAsmPrinter.cpp

Move alignment from MCSectionData to MCSection.

2015-05-21 19:20:38 +00:00

AMDGPUAsmPrinter.h

R600/SI: Add some missing overrides

2015-04-08 02:07:05 +00:00

AMDGPUCallingConv.td

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AMDGPUFrameLowering.cpp

[ShrinkWrap] Add (a simplified version) of shrink-wrapping.

2015-05-05 17:38:16 +00:00

AMDGPUFrameLowering.h

[ShrinkWrap] Add (a simplified version) of shrink-wrapping.

2015-05-05 17:38:16 +00:00

AMDGPUInstrInfo.cpp

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AMDGPUInstrInfo.h

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AMDGPUInstrInfo.td

R600/SI: Remove explicit m0 operand from v_interp instructions

2015-05-12 15:00:46 +00:00

AMDGPUInstructions.td

R600/SI: Remove explicit m0 operand from DS instructions

2015-05-12 15:00:49 +00:00

AMDGPUIntrinsicInfo.cpp

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AMDGPUIntrinsicInfo.h

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AMDGPUIntrinsics.td

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AMDGPUISelDAGToDAG.cpp

R600/SI: Remove explicit m0 operand from DS instructions

2015-05-12 15:00:49 +00:00

AMDGPUISelLowering.cpp

R600: Add comments to subword private address load lowering code

2015-05-26 18:07:21 +00:00

AMDGPUISelLowering.h

Add target hook to allow merging stores of nonzero constants

2015-05-24 00:51:27 +00:00

AMDGPUMachineFunction.cpp

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AMDGPUMachineFunction.h

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AMDGPUMCInstLower.cpp

MC: Clean up MCExpr naming. NFC.

2015-05-30 01:25:56 +00:00

AMDGPUMCInstLower.h

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AMDGPUPromoteAlloca.cpp

Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced init only

2015-05-18 22:13:54 +00:00

AMDGPURegisterInfo.cpp

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AMDGPURegisterInfo.h

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AMDGPURegisterInfo.td

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AMDGPUSubtarget.cpp

R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips

2015-05-25 16:15:54 +00:00

AMDGPUSubtarget.h

R600: Re-enable sub-reg liveness

2015-06-04 01:20:04 +00:00

AMDGPUTargetMachine.cpp

R600/SI: add pass to mark CF live ranges as non-spillable

2015-05-12 17:13:02 +00:00

AMDGPUTargetMachine.h

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AMDGPUTargetTransformInfo.cpp

[X86] Disable loop unrolling in loop vectorization pass when VF is 1.

2015-05-06 17:12:25 +00:00

AMDGPUTargetTransformInfo.h

[X86] Disable loop unrolling in loop vectorization pass when VF is 1.

2015-05-06 17:12:25 +00:00

AMDILCFGStructurizer.cpp

CodeGen: Use the new DebugLoc API, NFC

2015-03-30 19:14:47 +00:00

AMDKernelCodeT.h

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CaymanInstructions.td

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CIInstructions.td

R600/SI: Add assembler support for all CI and VI VOP1 instructions

2015-04-23 19:33:54 +00:00

CMakeLists.txt

R600/SI: add pass to mark CF live ranges as non-spillable

2015-05-12 17:13:02 +00:00

EvergreenInstructions.td

Reinstate revisions r234755, r234759, r234760

2015-04-30 17:15:56 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips

2015-05-25 16:15:54 +00:00

R600ClauseMergePass.cpp

Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.

2015-03-23 19:32:43 +00:00

R600ControlFlowFinalizer.cpp

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R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

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R600InstrFormats.td

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R600InstrInfo.cpp

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R600InstrInfo.h

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R600Instructions.td

R600: Make FMIN/MAXNUM legal on all asics

2015-04-12 23:45:05 +00:00

R600Intrinsics.td

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R600ISelLowering.cpp

R600: Rely on TypeLegalizer to use divrem instead of div/rem

2015-05-27 16:54:10 +00:00

R600ISelLowering.h

Reinstate revisions r234755, r234759, r234760

2015-04-30 17:15:56 +00:00

R600MachineFunctionInfo.cpp

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R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.

2015-03-23 19:32:43 +00:00

R600Packetizer.cpp

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R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

Reduce dyn_cast<> to isa<> or cast<> where possible.

2015-04-10 11:24:51 +00:00

R700Instructions.td

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SIAnnotateControlFlow.cpp

R600/SI: Fix verifier errors from the SIAnnotateControlFlow pass

2015-05-01 03:44:08 +00:00

SIDefines.h

R600/SI: Fix bug in VGPR spilling

2015-05-12 18:59:17 +00:00

SIFixControlFlowLiveIntervals.cpp

R600/SI: add pass to mark CF live ranges as non-spillable

2015-05-12 17:13:02 +00:00

SIFixSGPRCopies.cpp

R600/SI: Remove M0Reg register class

2015-05-12 15:00:52 +00:00

SIFixSGPRLiveRanges.cpp

Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used.

2015-03-23 19:32:43 +00:00

SIFoldOperands.cpp

R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)

2015-05-12 14:18:11 +00:00

SIInsertWaits.cpp

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SIInstrFormats.td

R600/SI: Fix bug in VGPR spilling

2015-05-12 18:59:17 +00:00

SIInstrInfo.cpp

R600/SI: Fix verifier error when producing v_madmk_f32

2015-04-24 01:57:58 +00:00

SIInstrInfo.h

R600/SI: Fix bug in VGPR spilling

2015-05-12 18:59:17 +00:00

SIInstrInfo.td

R600/SI: Add assembler support for all CI and VI VOP2 instructions

2015-05-26 15:55:52 +00:00

SIInstructions.td

R600/SI: Add assembler support for all CI and VI VOP2 instructions

2015-05-26 15:55:52 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

R600/SI: Don't hardcode pointer type

2015-06-01 21:58:24 +00:00

SIISelLowering.h

Add address space argument to isLegalAddressingMode

2015-06-01 05:31:59 +00:00

SILoadStoreOptimizer.cpp

R600/SI: Remove explicit m0 operand from DS instructions

2015-05-12 15:00:49 +00:00

SILowerControlFlow.cpp

R600/SI: Fix indirect addressing with a negative constant offset

2015-04-23 20:32:01 +00:00

SILowerI1Copies.cpp

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SIMachineFunctionInfo.cpp

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SIMachineFunctionInfo.h

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SIPrepareScratchRegs.cpp

R600/SI: Fix bug in VGPR spilling

2015-05-12 18:59:17 +00:00

SIRegisterInfo.cpp

R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0

2015-05-12 15:00:53 +00:00

SIRegisterInfo.h

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SIRegisterInfo.td

R600/SI: Remove M0Reg register class

2015-05-12 15:00:52 +00:00

SISchedule.td

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SIShrinkInstructions.cpp

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SITypeRewriter.cpp

Remove more superfluous .str() and replace std::string concatenation with Twine.

2015-03-30 15:42:36 +00:00

VIInstrFormats.td

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VIInstructions.td

R600/SI: Add assembler support for all CI and VI VOP2 instructions

2015-05-26 15:55:52 +00:00