mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-28 04:33:05 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
250 lines
8.7 KiB
ArmAsm
250 lines
8.7 KiB
ArmAsm
// RUN: llvm-mc -triple=arm64-linux-gnu -o - < %s | FileCheck %s
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// RUN: llvm-mc -triple=arm64-linux-gnu -filetype=obj < %s | llvm-objdump -triple=arm64-linux-gnu - -r | FileCheck %s --check-prefix=CHECK-OBJ
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add x0, x2, #:lo12:sym
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// CHECK: add x0, x2, :lo12:sym
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// CHECK-OBJ: 0 R_AARCH64_ADD_ABS_LO12_NC sym
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add x5, x7, #:dtprel_lo12:sym
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// CHECK: add x5, x7, :dtprel_lo12:sym
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// CHECK-OBJ: 4 R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym
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add x9, x12, #:dtprel_lo12_nc:sym
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// CHECK: add x9, x12, :dtprel_lo12_nc:sym
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// CHECK-OBJ: 8 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym
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add x20, x30, #:tprel_lo12:sym
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// CHECK: add x20, lr, :tprel_lo12:sym
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// CHECK-OBJ: c R_AARCH64_TLSLE_ADD_TPREL_LO12 sym
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add x9, x12, #:tprel_lo12_nc:sym
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// CHECK: add x9, x12, :tprel_lo12_nc:sym
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// CHECK-OBJ: 10 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym
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add x5, x0, #:tlsdesc_lo12:sym
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// CHECK: add x5, x0, :tlsdesc_lo12:sym
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// CHECK-OBJ: 14 R_AARCH64_TLSDESC_ADD_LO12_NC sym
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add x0, x2, #:lo12:sym+8
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// CHECK: add x0, x2, :lo12:sym
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// CHECK-OBJ: 18 R_AARCH64_ADD_ABS_LO12_NC sym+8
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add x5, x7, #:dtprel_lo12:sym+1
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// CHECK: add x5, x7, :dtprel_lo12:sym+1
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// CHECK-OBJ: 1c R_AARCH64_TLSLD_ADD_DTPREL_LO12 sym+1
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add x9, x12, #:dtprel_lo12_nc:sym+2
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// CHECK: add x9, x12, :dtprel_lo12_nc:sym+2
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// CHECK-OBJ:20 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC sym+2
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add x20, x30, #:tprel_lo12:sym+12
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// CHECK: add x20, lr, :tprel_lo12:sym+12
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// CHECK-OBJ: 24 R_AARCH64_TLSLE_ADD_TPREL_LO12 sym+12
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add x9, x12, #:tprel_lo12_nc:sym+54
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// CHECK: add x9, x12, :tprel_lo12_nc:sym+54
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// CHECK-OBJ: 28 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC sym+54
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add x5, x0, #:tlsdesc_lo12:sym+70
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// CHECK: add x5, x0, :tlsdesc_lo12:sym+70
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// CHECK-OBJ: 2c R_AARCH64_TLSDESC_ADD_LO12_NC sym+70
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.hword sym + 4 - .
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// CHECK-OBJ: 30 R_AARCH64_PREL16 sym+4
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.word sym - . + 8
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// CHECK-OBJ: 32 R_AARCH64_PREL32 sym+8
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.xword sym-.
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// CHECK-OBJ: 36 R_AARCH64_PREL64 sym{{$}}
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.hword sym
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// CHECK-OBJ: 3e R_AARCH64_ABS16 sym
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.word sym+1
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// CHECK-OBJ: 40 R_AARCH64_ABS32 sym+1
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.xword sym+16
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// CHECK-OBJ: 44 R_AARCH64_ABS64 sym+16
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adrp x0, sym
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// CHECK: adrp x0, sym
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// CHECK-OBJ: 4c R_AARCH64_ADR_PREL_PG_HI21 sym
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adrp x15, :got:sym
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// CHECK: adrp x15, :got:sym
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// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
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adrp x29, :gottprel:sym
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// CHECK: adrp fp, :gottprel:sym
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// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
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adrp x2, :tlsdesc:sym
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// CHECK: adrp x2, :tlsdesc:sym
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// CHECK-OBJ: 58 R_AARCH64_TLSDESC_ADR_PAGE sym
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// LLVM is not competent enough to do this relocation because the
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// page boundary could occur anywhere after linking. A relocation
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// is needed.
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adrp x3, trickQuestion
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.global trickQuestion
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trickQuestion:
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// CHECK: adrp x3, trickQuestion
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// CHECK-OBJ: 5c R_AARCH64_ADR_PREL_PG_HI21 trickQuestion
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ldrb w2, [x3, #:lo12:sym]
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ldrsb w5, [x7, #:lo12:sym]
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ldrsb x11, [x13, #:lo12:sym]
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ldr b17, [x19, #:lo12:sym]
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// CHECK: ldrb w2, [x3, :lo12:sym]
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// CHECK: ldrsb w5, [x7, :lo12:sym]
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// CHECK: ldrsb x11, [x13, :lo12:sym]
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// CHECK: ldr b17, [x19, :lo12:sym]
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// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST8_ABS_LO12_NC sym
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ldrb w23, [x29, #:dtprel_lo12_nc:sym]
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ldrsb w23, [x19, #:dtprel_lo12:sym]
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ldrsb x17, [x13, #:dtprel_lo12_nc:sym]
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ldr b11, [x7, #:dtprel_lo12:sym]
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// CHECK: ldrb w23, [fp, :dtprel_lo12_nc:sym]
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// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
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// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
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// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 sym
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ldrb w1, [x2, #:tprel_lo12:sym]
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ldrsb w3, [x4, #:tprel_lo12_nc:sym]
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ldrsb x5, [x6, #:tprel_lo12:sym]
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ldr b7, [x8, #:tprel_lo12_nc:sym]
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// CHECK: ldrb w1, [x2, :tprel_lo12:sym]
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// CHECK: ldrsb w3, [x4, :tprel_lo12_nc:sym]
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// CHECK: ldrsb x5, [x6, :tprel_lo12:sym]
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// CHECK: ldr b7, [x8, :tprel_lo12_nc:sym]
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC sym
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ldrh w2, [x3, #:lo12:sym]
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ldrsh w5, [x7, #:lo12:sym]
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ldrsh x11, [x13, #:lo12:sym]
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ldr h17, [x19, #:lo12:sym]
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// CHECK: ldrh w2, [x3, :lo12:sym]
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// CHECK: ldrsh w5, [x7, :lo12:sym]
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// CHECK: ldrsh x11, [x13, :lo12:sym]
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// CHECK: ldr h17, [x19, :lo12:sym]
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// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST16_ABS_LO12_NC sym
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ldrh w23, [x29, #:dtprel_lo12_nc:sym]
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ldrsh w23, [x19, #:dtprel_lo12:sym]
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ldrsh x17, [x13, #:dtprel_lo12_nc:sym]
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ldr h11, [x7, #:dtprel_lo12:sym]
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// CHECK: ldrh w23, [fp, :dtprel_lo12_nc:sym]
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// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
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// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
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// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 sym
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ldrh w1, [x2, #:tprel_lo12:sym]
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ldrsh w3, [x4, #:tprel_lo12_nc:sym]
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ldrsh x5, [x6, #:tprel_lo12:sym]
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ldr h7, [x8, #:tprel_lo12_nc:sym]
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// CHECK: ldrh w1, [x2, :tprel_lo12:sym]
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// CHECK: ldrsh w3, [x4, :tprel_lo12_nc:sym]
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// CHECK: ldrsh x5, [x6, :tprel_lo12:sym]
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// CHECK: ldr h7, [x8, :tprel_lo12_nc:sym]
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC sym
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ldr w1, [x2, #:lo12:sym]
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ldrsw x3, [x4, #:lo12:sym]
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ldr s4, [x5, #:lo12:sym]
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// CHECK: ldr w1, [x2, :lo12:sym]
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// CHECK: ldrsw x3, [x4, :lo12:sym]
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// CHECK: ldr s4, [x5, :lo12:sym]
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// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST32_ABS_LO12_NC sym
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ldr w1, [x2, #:dtprel_lo12:sym]
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ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
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ldr s4, [x5, #:dtprel_lo12_nc:sym]
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// CHECK: ldr w1, [x2, :dtprel_lo12:sym]
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// CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
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// CHECK: ldr s4, [x5, :dtprel_lo12_nc:sym]
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC sym
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ldr w1, [x2, #:tprel_lo12:sym]
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ldrsw x3, [x4, #:tprel_lo12_nc:sym]
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ldr s4, [x5, #:tprel_lo12_nc:sym]
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// CHECK: ldr w1, [x2, :tprel_lo12:sym]
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// CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
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// CHECK: ldr s4, [x5, :tprel_lo12_nc:sym]
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC sym
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ldr x28, [x27, #:lo12:sym]
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ldr d26, [x25, #:lo12:sym]
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// CHECK: ldr x28, [x27, :lo12:sym]
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// CHECK: ldr d26, [x25, :lo12:sym]
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// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LDST64_ABS_LO12_NC sym
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ldr x24, [x23, #:got_lo12:sym]
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ldr d22, [x21, #:got_lo12:sym]
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// CHECK: ldr x24, [x23, :got_lo12:sym]
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// CHECK: ldr d22, [x21, :got_lo12:sym]
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// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_LD64_GOT_LO12_NC sym
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ldr x24, [x23, #:dtprel_lo12_nc:sym]
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ldr d22, [x21, #:dtprel_lo12:sym]
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// CHECK: ldr x24, [x23, :dtprel_lo12_nc:sym]
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// CHECK: ldr d22, [x21, :dtprel_lo12:sym]
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 sym
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ldr x24, [x23, #:tprel_lo12:sym]
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ldr d22, [x21, #:tprel_lo12_nc:sym]
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// CHECK: ldr x24, [x23, :tprel_lo12:sym]
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// CHECK: ldr d22, [x21, :tprel_lo12_nc:sym]
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12 sym
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// CHECK-OBJ: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC sym
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ldr x24, [x23, #:gottprel_lo12:sym]
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ldr d22, [x21, #:gottprel_lo12:sym]
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// CHECK: ldr x24, [x23, :gottprel_lo12:sym]
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// CHECK: ldr d22, [x21, :gottprel_lo12:sym]
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// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC sym
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ldr x24, [x23, #:tlsdesc_lo12:sym]
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ldr d22, [x21, #:tlsdesc_lo12:sym]
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// CHECK: ldr x24, [x23, :tlsdesc_lo12:sym]
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// CHECK: ldr d22, [x21, :tlsdesc_lo12:sym]
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// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
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// CHECK-OBJ: R_AARCH64_TLSDESC_LD64_LO12_NC sym
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ldr q20, [x19, #:lo12:sym]
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// CHECK: ldr q20, [x19, :lo12:sym]
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// CHECK-OBJ: R_AARCH64_LDST128_ABS_LO12_NC sym
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// Since relocated instructions print without a '#', that syntax should
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// certainly be accepted when assembling.
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add x3, x5, :lo12:imm
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// CHECK: add x3, x5, :lo12:imm
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