Andrew Trick 1c2d3c538c sched: fix latency of memory dependence chain edges for consistency. ...

For store->load dependencies that may alias, we should always use
TrueMemOrderLatency, which may eventually become a subtarget hook. In
effect, we should guarantee at least TrueMemOrderLatency on at least
one DAG path from a store to a may-alias load.

This should fix the standard mode as well as -enable-aa-sched-mi".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158380 91177308-0d34-0410-b5e6-96231b3b80d8

2012-06-13 02:39:03 +00:00

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ARM

sched: fix latency of memory dependence chain edges for consistency.

2012-06-13 02:39:03 +00:00

CellSPU

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CPP

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Generic

Fix test case to work on ARM.

2012-06-11 16:01:14 +00:00

Hexagon

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MBlaze

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Mips

Add a test case for mips64 unaligned load/store instructions.

2012-06-04 17:57:06 +00:00

MSP430

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NVPTX

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PowerPC

Enable ILP scheduling for all nodes by default on PPC.

2012-06-10 19:32:29 +00:00

SPARC

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Thumb

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Thumb2

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X86

Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an argument.

2012-06-09 16:46:13 +00:00

XCore

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