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llvm-6502/test/CodeGen/ARM/fast-isel-br-phi.ll
Jim Grosbach 383a810b12 ARM: Constrain regclass for TSTri instruction. 
Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-26 20:22:05 +00:00

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