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https://github.com/c64scene-ar/llvm-6502.git
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afb1938c39
We were assuming all SBFX-like operations would have the shl/asr form, but often when the field being extracted is an i8 or i16, we end up with a SIGN_EXTEND_INREG acting on a shift instead. Simple enough to check for though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213754 91177308-0d34-0410-b5e6-96231b3b80d8
66 lines
1.1 KiB
LLVM
66 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s
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define i32 @f1(i32 %a) {
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entry:
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; CHECK-LABEL: f1:
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; CHECK: sbfx r0, r0, #0, #20
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%tmp = shl i32 %a, 12
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%tmp2 = ashr i32 %tmp, 12
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ret i32 %tmp2
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}
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define i32 @f2(i32 %a) {
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entry:
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; CHECK-LABEL: f2:
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; CHECK: bfc r0, #20, #12
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%tmp = shl i32 %a, 12
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%tmp2 = lshr i32 %tmp, 12
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ret i32 %tmp2
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}
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define i32 @f3(i32 %a) {
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entry:
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; CHECK-LABEL: f3:
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; CHECK: sbfx r0, r0, #5, #3
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%tmp = shl i32 %a, 24
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%tmp2 = ashr i32 %tmp, 29
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ret i32 %tmp2
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}
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define i32 @f4(i32 %a) {
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entry:
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; CHECK-LABEL: f4:
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; CHECK: ubfx r0, r0, #5, #3
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%tmp = shl i32 %a, 24
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%tmp2 = lshr i32 %tmp, 29
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ret i32 %tmp2
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}
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define i32 @f5(i32 %a) {
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entry:
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; CHECK-LABEL: f5:
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; CHECK-NOT: sbfx
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; CHECK: bx
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%tmp = shl i32 %a, 3
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%tmp2 = ashr i32 %tmp, 1
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ret i32 %tmp2
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}
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define signext i8 @f6(i32 %a) {
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; CHECK-LABEL: f6:
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; CHECK: sbfx r0, r0, #23, #8
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%tmp = lshr i32 %a, 23
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%res = trunc i32 %tmp to i8
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ret i8 %res
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}
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define signext i8 @f7(i32 %a) {
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; CHECK-LABEL: f7:
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; CHECK-NOT: sbfx
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%tmp = lshr i32 %a, 25
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%res = trunc i32 %tmp to i8
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ret i8 %res
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}
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