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36e5511188
Some of these tests did not specify a cpu but were also sensitive to instruction scheduling and/or register assignment choices. A few others similarly-sensitive tests specified a cpu (often the POWER7), and while the P7 currently uses the default model for PPC64, this will soon change. For those tests which should not really be cpu-dependent anyway, the cpu is set to the generic 'ppc64'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195977 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
646 B
LLVM
19 lines
646 B
LLVM
; RUN: llc -march=ppc64 -mcpu=g5 -mtriple=powerpc64-apple-darwin < %s | FileCheck %s
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; Check that the peephole optimizer knows about sext and zext instructions.
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; CHECK: test1sext
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define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
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%C = add i64 %A, %B
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; CHECK: add [[SUM:r[0-9]+]], r3, r4
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%D = trunc i64 %C to i32
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%E = shl i64 %C, 32
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%F = ashr i64 %E, 32
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; CHECK: extsw [[EXT:r[0-9]+]], [[SUM]]
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store volatile i64 %F, i64 *%P2
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; CHECK: std [[EXT]]
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store volatile i32 %D, i32* %P
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; Reuse low bits of extended register, don't extend live range of SUM.
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; CHECK: stw [[EXT]]
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%R = add i32 %D, %D
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ret i32 %R
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}
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