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https://github.com/c64scene-ar/llvm-6502.git
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1ef2cec146
The PowerPC 128-bit long double data type (ppcf128 in LLVM) is in fact a pair of two doubles, where one is considered the "high" or more-significant part, and the other is considered the "low" or less-significant part. When a ppcf128 value is stored in memory or a register pair, the high part always comes first, i.e. at the lower memory address or in the lower-numbered register, and the low part always comes second. This is true both on big-endian and little-endian PowerPC systems. (Similar to how with a complex number, the real part always comes first and the imaginary part second, no matter the byte order of the system.) This was implemented incorrectly for little-endian systems in LLVM. This commit fixes three related issues: - When printing an immediate ppcf128 constant to assembler output in emitGlobalConstantFP, emit the high part first on both big- and little-endian systems. - When lowering a ppcf128 type to a pair of f64 types in SelectionDAG (which is used e.g. when generating code to load an argument into a register pair), use correct low/high part ordering on little-endian systems. - In a related issue, because lowering ppcf128 into a pair of f64 must operate differently from lowering an int128 into a pair of i64, bitcasts between ppcf128 and int128 must not be optimized away by the DAG combiner on little-endian systems, but must effect a word-swap. Reviewed by Hal Finkel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212274 91177308-0d34-0410-b5e6-96231b3b80d8
155 lines
3.4 KiB
LLVM
155 lines
3.4 KiB
LLVM
; RUN: llc -mcpu=pwr7 -mattr=+altivec < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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@g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
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define void @callee(ppc_fp128 %x) {
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entry:
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%x.addr = alloca ppc_fp128, align 16
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store ppc_fp128 %x, ppc_fp128* %x.addr, align 16
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%0 = load ppc_fp128* %x.addr, align 16
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store ppc_fp128 %0, ppc_fp128* @g, align 16
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ret void
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}
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; CHECK: @callee
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: stfd 2, 8([[REG]])
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; CHECK: stfd 1, 0([[REG]])
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; CHECK: blr
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define void @caller() {
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entry:
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%0 = load ppc_fp128* @g, align 16
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call void @test(ppc_fp128 %0)
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ret void
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}
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; CHECK: @caller
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: lfd 2, 8([[REG]])
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; CHECK: lfd 1, 0([[REG]])
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; CHECK: bl test
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declare void @test(ppc_fp128)
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define void @caller_const() {
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entry:
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call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)
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ret void
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}
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; CHECK: .LCPI[[LC:[0-9]+]]_0:
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; CHECK: .long 1065353216
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; CHECK: .LCPI[[LC]]_1:
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; CHECK: .long 0
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; CHECK: @caller_const
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; CHECK: addi [[REG0:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_0
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; CHECK: addi [[REG1:[0-9]+]], {{[0-9]+}}, .LCPI[[LC]]_1
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; CHECK: lfs 1, 0([[REG0]])
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; CHECK: lfs 2, 0([[REG1]])
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; CHECK: bl test
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define ppc_fp128 @result() {
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entry:
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%0 = load ppc_fp128* @g, align 16
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ret ppc_fp128 %0
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}
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; CHECK: @result
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: lfd 1, 0([[REG]])
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; CHECK: lfd 2, 8([[REG]])
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; CHECK: blr
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define void @use_result() {
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entry:
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%call = tail call ppc_fp128 @test_result() #3
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store ppc_fp128 %call, ppc_fp128* @g, align 16
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ret void
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}
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; CHECK: @use_result
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; CHECK: bl test_result
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; CHECK: ld [[REG:[0-9]+]], .LC
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; CHECK: stfd 2, 8([[REG]])
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; CHECK: stfd 1, 0([[REG]])
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; CHECK: blr
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declare ppc_fp128 @test_result()
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define void @caller_result() {
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entry:
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%call = tail call ppc_fp128 @test_result()
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tail call void @test(ppc_fp128 %call)
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ret void
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}
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; CHECK: @caller_result
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; CHECK: bl test_result
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl test
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; CHECK-NEXT: nop
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define i128 @convert_from(ppc_fp128 %x) {
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entry:
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%0 = bitcast ppc_fp128 %x to i128
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ret i128 %0
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}
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; CHECK: @convert_from
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; CHECK: stfd 1, [[OFF1:.*]](1)
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; CHECK: stfd 2, [[OFF2:.*]](1)
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; CHECK: ld 3, [[OFF1]](1)
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; CHECK: ld 4, [[OFF2]](1)
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; CHECK: blr
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define ppc_fp128 @convert_to(i128 %x) {
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entry:
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%0 = bitcast i128 %x to ppc_fp128
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ret ppc_fp128 %0
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}
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; CHECK: @convert_to
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; CHECK: std 3, [[OFF1:.*]](1)
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; CHECK: std 4, [[OFF2:.*]](1)
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; CHECK: lfd 1, [[OFF1]](1)
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; CHECK: lfd 2, [[OFF2]](1)
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; CHECK: blr
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define ppc_fp128 @convert_to2(i128 %x) {
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entry:
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%shl = shl i128 %x, 1
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%0 = bitcast i128 %shl to ppc_fp128
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ret ppc_fp128 %0
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}
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; CHECK: @convert_to
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; CHECK: std 3, [[OFF1:.*]](1)
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; CHECK: std 4, [[OFF2:.*]](1)
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; CHECK: lfd 1, [[OFF1]](1)
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; CHECK: lfd 2, [[OFF2]](1)
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; CHECK: blr
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define double @convert_vector(<4 x i32> %x) {
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entry:
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%cast = bitcast <4 x i32> %x to ppc_fp128
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%conv = fptrunc ppc_fp128 %cast to double
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ret double %conv
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}
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; CHECK: @convert_vector
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; CHECK: addi [[REG:[0-9]+]], 1, [[OFF:.*]]
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; CHECK: stvx 2, 0, [[REG]]
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; CHECK: lfd 1, [[OFF]](1)
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; CHECK: blr
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declare void @llvm.va_start(i8*)
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define double @vararg(i32 %a, ...) {
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entry:
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%va = alloca i8*, align 8
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%va1 = bitcast i8** %va to i8*
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call void @llvm.va_start(i8* %va1)
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%arg = va_arg i8** %va, ppc_fp128
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%conv = fptrunc ppc_fp128 %arg to double
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ret double %conv
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}
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; CHECK: @vararg
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; CHECK: lfd 1, 0({{[0-9]+}})
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; CHECK: blr
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