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11729224bf
This is a preliminary patch for fast instruction selection on PowerPC. Code generation can differ between DAG isel and fast isel. Existing tests that specify -O0 were written to expect DAG isel. Make this explicit by adding -fast-isel=false to the tests. In some cases specifying -fast-isel=false produces different code even when there isn't a fast instruction selector specified. This is because TM.Options.EnableFastISel = 1 at -O0 whether or not a FastISel object exists. Thus disabling fast isel can actually produce less conservative code. Because of this, some of the expected code generation in the -O0 tests needs to be adjusted. In particular, handling of function arguments is less conservative with -fast-isel=false (see isOnlyUsedInEntryBlock() in SelectionDAGBuilder.cpp). This results in fewer stack accesses and, in some cases, reduced stack size as uselessly loaded values are no longer stored back to spill locations in the stack. No functional change with this patch; test case adjustments only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183939 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
631 B
LLVM
19 lines
631 B
LLVM
; RUN: llc -O0 -mtriple=powerpc-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -verify-machineinstrs -fast-isel=false < %s | FileCheck %s
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; This verifies that we generate correct spill/reload code for vector regs.
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define void @addrtaken(i32 %i, <4 x float> %w) nounwind {
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entry:
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%i.addr = alloca i32, align 4
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%w.addr = alloca <4 x float>, align 16
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store i32 %i, i32* %i.addr, align 4
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store <4 x float> %w, <4 x float>* %w.addr, align 16
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call void @foo(i32* %i.addr)
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ret void
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}
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; CHECK: stvx 2,
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declare void @foo(i32*)
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