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1f65cfad96
Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200957 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
646 B
LLVM
23 lines
646 B
LLVM
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.1 | FileCheck %s -check-prefix=SSE41
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; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+avx | FileCheck %s -check-prefix=AVX
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define void @pextrb(i8* nocapture %dst, <16 x i8> %foo) {
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; AVX: vpextrb
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; SSE41: pextrb
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; AVX-NOT: movb
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; SSE41-NOT: movb
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%vecext = extractelement <16 x i8> %foo, i32 15
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store i8 %vecext, i8* %dst, align 1
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ret void
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}
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define void @pextrw(i16* nocapture %dst, <8 x i16> %foo) {
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; AVX: vpextrw
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; SSE41: pextrw
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; AVX-NOT: movw
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; SSE41-NOT: movw
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%vecext = extractelement <8 x i16> %foo, i32 15
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store i16 %vecext, i16* %dst, align 1
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ret void
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}
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