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https://github.com/c64scene-ar/llvm-6502.git
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d47cb57ab8
This patch renames method 'isConstantSplat' as 'getConstantSplatValue' (mainly for consistency reasons), and rewrites its logic to ensure that we always perform a legal 'cast<ConstantSDNode>'. Added test shift-combine-crash.ll to verify that DAGCombiner no longer crashes with an assertion failure in the attempt to simplify a vector shift by a vector of all undef counts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204536 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.7 KiB
LLVM
58 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 > /dev/null
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; Verify that DAGCombiner doesn't crash with an assertion failure in the
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; attempt to cast a ISD::UNDEF node to a ConstantSDNode.
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; During type legalization, the vector shift operation in function @test1 is
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; split into two legal shifts that work on <2 x i64> elements.
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; The first shift of the legalized sequence would be a shift by all undefs.
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; DAGCombiner will then try to simplify the vector shift and check if the
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; vector of shift counts is a splat. Make sure that llc doesn't crash
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; at that stage.
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define <4 x i64> @test1(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 1, i64 2>
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ret <4 x i64> %shl
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}
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; Also, verify that DAGCombiner doesn't crash when trying to combine shifts
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; with different combinations of undef elements in the vector shift count.
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define <4 x i64> @test2(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 2, i64 3, i64 undef, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test3(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 3, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test4(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 2, i64 undef, i64 3>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test5(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 2, i64 undef, i64 undef, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test6(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 3, i64 undef>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test7(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 3>
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ret <4 x i64> %shl
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}
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define <4 x i64> @test8(<4 x i64> %A) {
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%shl = shl <4 x i64> %A, <i64 undef, i64 undef, i64 undef, i64 undef>
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ret <4 x i64> %shl
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}
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