mirror of
https://github.com/c64scene-ar/llvm-6502.git
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228a18e0f2
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms, a 33% speedup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29743 91177308-0d34-0410-b5e6-96231b3b80d8
903 lines
29 KiB
C++
903 lines
29 KiB
C++
//===----- ScheduleDAGList.cpp - Reg pressure reduction list scheduler ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Evan Cheng and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements bottom-up and top-down register pressure reduction list
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// schedulers, using standard algorithms. The basic approach uses a priority
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// queue of available nodes to schedule. One at a time, nodes are taken from
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// the priority queue (thus in priority order), checked for legality to
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// schedule, and emitted if legal.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Visibility.h"
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#include "llvm/ADT/Statistic.h"
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#include <climits>
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#include <iostream>
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#include <queue>
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static RegisterScheduler
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burrListDAGScheduler("list-burr",
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" Bottom-up register reduction list scheduling",
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createBURRListDAGScheduler);
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static RegisterScheduler
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tdrListrDAGScheduler("list-tdrr",
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" Top-down register reduction list scheduling",
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createTDRRListDAGScheduler);
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namespace {
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//===----------------------------------------------------------------------===//
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/// ScheduleDAGRRList - The actual register reduction list scheduler
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/// implementation. This supports both top-down and bottom-up scheduling.
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///
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class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
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private:
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/// isBottomUp - This is true if the scheduling problem is bottom-up, false if
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/// it is top-down.
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bool isBottomUp;
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/// AvailableQueue - The priority queue to use for the available SUnits.
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///
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SchedulingPriorityQueue *AvailableQueue;
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public:
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ScheduleDAGRRList(SelectionDAG &dag, MachineBasicBlock *bb,
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const TargetMachine &tm, bool isbottomup,
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SchedulingPriorityQueue *availqueue)
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: ScheduleDAG(dag, bb, tm), isBottomUp(isbottomup),
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AvailableQueue(availqueue) {
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}
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~ScheduleDAGRRList() {
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delete AvailableQueue;
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}
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void Schedule();
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private:
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void ReleasePred(SUnit *PredSU, bool isChain, unsigned CurCycle);
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void ReleaseSucc(SUnit *SuccSU, bool isChain, unsigned CurCycle);
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void ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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void ListScheduleBottomUp();
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void CommuteNodesToReducePressure();
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};
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} // end anonymous namespace
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/// Schedule - Schedule the DAG using list scheduling.
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void ScheduleDAGRRList::Schedule() {
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DEBUG(std::cerr << "********** List Scheduling **********\n");
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// Build scheduling units.
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BuildSchedUnits();
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CalculateDepths();
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CalculateHeights();
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(&DAG));
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AvailableQueue->initNodes(SUnits);
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// Execute the actual scheduling loop Top-Down or Bottom-Up as appropriate.
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if (isBottomUp)
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ListScheduleBottomUp();
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else
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ListScheduleTopDown();
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AvailableQueue->releaseState();
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CommuteNodesToReducePressure();
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DEBUG(std::cerr << "*** Final schedule ***\n");
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DEBUG(dumpSchedule());
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DEBUG(std::cerr << "\n");
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// Emit in scheduled order
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EmitSchedule();
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}
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/// CommuteNodesToReducePressure - Is a node is two-address and commutable, and
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/// it is not the last use of its first operand, add it to the CommuteSet if
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/// possible. It will be commuted when it is translated to a MI.
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void ScheduleDAGRRList::CommuteNodesToReducePressure() {
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std::set<SUnit *> OperandSeen;
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for (unsigned i = Sequence.size()-1; i != 0; --i) { // Ignore first node.
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SUnit *SU = Sequence[i];
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if (!SU) continue;
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if (SU->isTwoAddress && SU->isCommutable) {
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SDNode *OpN = SU->Node->getOperand(0).Val;
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SUnit *OpSU = SUnitMap[OpN];
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if (OpSU && OperandSeen.count(OpSU) == 1) {
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// Ok, so SU is not the last use of OpSU, but SU is two-address so
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// it will clobber OpSU. Try to commute it if possible.
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bool DoCommute = true;
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for (unsigned j = 1, e = SU->Node->getNumOperands(); j != e; ++j) {
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OpN = SU->Node->getOperand(j).Val;
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OpSU = SUnitMap[OpN];
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if (OpSU && OperandSeen.count(OpSU) == 1) {
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DoCommute = false;
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break;
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}
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}
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if (DoCommute)
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CommuteSet.insert(SU->Node);
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}
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}
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (!I->second)
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OperandSeen.insert(I->first);
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Bottom-Up Scheduling
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//===----------------------------------------------------------------------===//
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static const TargetRegisterClass *getRegClass(SUnit *SU,
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const TargetInstrInfo *TII,
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const MRegisterInfo *MRI,
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SSARegMap *RegMap) {
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if (SU->Node->isTargetOpcode()) {
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unsigned Opc = SU->Node->getTargetOpcode();
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const TargetInstrDescriptor &II = TII->get(Opc);
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return MRI->getRegClass(II.OpInfo->RegClass);
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} else {
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assert(SU->Node->getOpcode() == ISD::CopyFromReg);
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unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
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if (MRegisterInfo::isVirtualRegister(SrcReg))
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return RegMap->getRegClass(SrcReg);
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else {
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for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
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E = MRI->regclass_end(); I != E; ++I)
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if ((*I)->hasType(SU->Node->getValueType(0)) &&
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(*I)->contains(SrcReg))
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return *I;
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assert(false && "Couldn't find register class for reg copy!");
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}
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return NULL;
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}
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}
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static unsigned getNumResults(SUnit *SU) {
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unsigned NumResults = 0;
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for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
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MVT::ValueType VT = SU->Node->getValueType(i);
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if (VT != MVT::Other && VT != MVT::Flag)
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NumResults++;
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}
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return NumResults;
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}
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/// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
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/// the Available queue is the count reaches zero. Also update its cycle bound.
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void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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PredSU->CycleBound = std::max(PredSU->CycleBound, CurCycle + PredSU->Latency);
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if (!isChain)
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PredSU->NumSuccsLeft--;
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else
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PredSU->NumChainSuccsLeft--;
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#ifndef NDEBUG
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if (PredSU->NumSuccsLeft < 0 || PredSU->NumChainSuccsLeft < 0) {
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std::cerr << "*** List scheduling failed! ***\n";
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PredSU->dump(&DAG);
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std::cerr << " has been released too many times!\n";
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assert(0);
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}
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#endif
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if ((PredSU->NumSuccsLeft + PredSU->NumChainSuccsLeft) == 0) {
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// EntryToken has to go last! Special case it here.
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if (PredSU->Node->getOpcode() != ISD::EntryToken) {
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PredSU->isAvailable = true;
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AvailableQueue->push(PredSU);
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}
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}
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}
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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AvailableQueue->ScheduledNode(SU);
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Sequence.push_back(SU);
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// Bottom up: release predecessors
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for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I)
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ReleasePred(I->first, I->second, CurCycle);
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SU->isScheduled = true;
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}
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/// isReady - True if node's lower cycle bound is less or equal to the current
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/// scheduling cycle. Always true if all nodes have uniform latency 1.
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static inline bool isReady(SUnit *SU, unsigned CurCycle) {
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return SU->CycleBound <= CurCycle;
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}
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/// ListScheduleBottomUp - The main loop of list scheduling for bottom-up
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/// schedulers.
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void ScheduleDAGRRList::ListScheduleBottomUp() {
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unsigned CurCycle = 0;
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// Add root to Available queue.
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AvailableQueue->push(SUnitMap[DAG.getRoot().Val]);
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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SUnit *CurNode = NULL;
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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while (CurNode && !isReady(CurNode, CurCycle)) {
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NotReady.push_back(CurNode);
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CurNode = AvailableQueue->pop();
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}
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// Add the nodes that aren't ready back onto the available list.
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AvailableQueue->push_all(NotReady);
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NotReady.clear();
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if (CurNode != NULL)
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ScheduleNodeBottomUp(CurNode, CurCycle);
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CurCycle++;
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}
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// Add entry node last
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if (DAG.getEntryNode().Val != DAG.getRoot().Val) {
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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Sequence.push_back(Entry);
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}
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// Reverse the order if it is bottom up.
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std::reverse(Sequence.begin(), Sequence.end());
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#ifndef NDEBUG
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// Verify that all SUnits were scheduled.
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bool AnyNotSched = false;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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if (SUnits[i].NumSuccsLeft != 0 || SUnits[i].NumChainSuccsLeft != 0) {
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if (!AnyNotSched)
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std::cerr << "*** List scheduling failed! ***\n";
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SUnits[i].dump(&DAG);
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std::cerr << "has not been scheduled!\n";
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AnyNotSched = true;
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}
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}
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assert(!AnyNotSched);
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#endif
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}
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//===----------------------------------------------------------------------===//
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// Top-Down Scheduling
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//===----------------------------------------------------------------------===//
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
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/// the PendingQueue if the count reaches zero.
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void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
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unsigned CurCycle) {
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// FIXME: the distance between two nodes is not always == the predecessor's
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// latency. For example, the reader can very well read the register written
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// by the predecessor later than the issue cycle. It also depends on the
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// interrupt model (drain vs. freeze).
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SuccSU->CycleBound = std::max(SuccSU->CycleBound, CurCycle + SuccSU->Latency);
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if (!isChain)
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SuccSU->NumPredsLeft--;
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else
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SuccSU->NumChainPredsLeft--;
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft < 0 || SuccSU->NumChainPredsLeft < 0) {
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std::cerr << "*** List scheduling failed! ***\n";
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SuccSU->dump(&DAG);
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std::cerr << " has been released too many times!\n";
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assert(0);
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}
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#endif
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if ((SuccSU->NumPredsLeft + SuccSU->NumChainPredsLeft) == 0) {
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SuccSU->isAvailable = true;
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AvailableQueue->push(SuccSU);
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}
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}
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/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
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/// count of its successors. If a successor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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AvailableQueue->ScheduledNode(SU);
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Sequence.push_back(SU);
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// Top down: release successors
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for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
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I != E; ++I)
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ReleaseSucc(I->first, I->second, CurCycle);
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SU->isScheduled = true;
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}
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void ScheduleDAGRRList::ListScheduleTopDown() {
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unsigned CurCycle = 0;
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SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
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// All leaves to Available queue.
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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// It is available if it has no predecessors.
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if (SUnits[i].Preds.size() == 0 && &SUnits[i] != Entry) {
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AvailableQueue->push(&SUnits[i]);
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SUnits[i].isAvailable = true;
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}
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}
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// Emit the entry node first.
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ScheduleNodeTopDown(Entry, CurCycle);
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CurCycle++;
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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std::vector<SUnit*> NotReady;
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SUnit *CurNode = NULL;
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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while (CurNode && !isReady(CurNode, CurCycle)) {
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NotReady.push_back(CurNode);
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CurNode = AvailableQueue->pop();
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}
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// Add the nodes that aren't ready back onto the available list.
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AvailableQueue->push_all(NotReady);
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NotReady.clear();
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if (CurNode != NULL)
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ScheduleNodeTopDown(CurNode, CurCycle);
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CurCycle++;
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}
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#ifndef NDEBUG
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// Verify that all SUnits were scheduled.
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bool AnyNotSched = false;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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if (!SUnits[i].isScheduled) {
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if (!AnyNotSched)
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std::cerr << "*** List scheduling failed! ***\n";
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SUnits[i].dump(&DAG);
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std::cerr << "has not been scheduled!\n";
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AnyNotSched = true;
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}
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}
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assert(!AnyNotSched);
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#endif
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}
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//===----------------------------------------------------------------------===//
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// RegReductionPriorityQueue Implementation
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//===----------------------------------------------------------------------===//
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//
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// This is a SchedulingPriorityQueue that schedules using Sethi Ullman numbers
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// to reduce register pressure.
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//
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namespace {
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template<class SF>
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class RegReductionPriorityQueue;
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/// Sorting functions for the Available queue.
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struct bu_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
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RegReductionPriorityQueue<bu_ls_rr_sort> *SPQ;
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bu_ls_rr_sort(RegReductionPriorityQueue<bu_ls_rr_sort> *spq) : SPQ(spq) {}
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bu_ls_rr_sort(const bu_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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struct td_ls_rr_sort : public std::binary_function<SUnit*, SUnit*, bool> {
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RegReductionPriorityQueue<td_ls_rr_sort> *SPQ;
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td_ls_rr_sort(RegReductionPriorityQueue<td_ls_rr_sort> *spq) : SPQ(spq) {}
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td_ls_rr_sort(const td_ls_rr_sort &RHS) : SPQ(RHS.SPQ) {}
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bool operator()(const SUnit* left, const SUnit* right) const;
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};
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} // end anonymous namespace
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namespace {
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template<class SF>
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class VISIBILITY_HIDDEN RegReductionPriorityQueue
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: public SchedulingPriorityQueue {
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std::priority_queue<SUnit*, std::vector<SUnit*>, SF> Queue;
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public:
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RegReductionPriorityQueue() :
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Queue(SF(this)) {}
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virtual void initNodes(std::vector<SUnit> &sunits) {}
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virtual void releaseState() {}
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virtual int getSethiUllmanNumber(unsigned NodeNum) const {
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return 0;
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}
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bool empty() const { return Queue.empty(); }
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void push(SUnit *U) {
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Queue.push(U);
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}
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void push_all(const std::vector<SUnit *> &Nodes) {
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for (unsigned i = 0, e = Nodes.size(); i != e; ++i)
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Queue.push(Nodes[i]);
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}
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SUnit *pop() {
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if (empty()) return NULL;
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SUnit *V = Queue.top();
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Queue.pop();
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return V;
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}
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};
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template<class SF>
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class VISIBILITY_HIDDEN BURegReductionPriorityQueue
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: public RegReductionPriorityQueue<SF> {
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// SUnits - The SUnits for the current graph.
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const std::vector<SUnit> *SUnits;
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// SethiUllmanNumbers - The SethiUllman number for each node.
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std::vector<int> SethiUllmanNumbers;
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public:
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BURegReductionPriorityQueue() {}
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void initNodes(std::vector<SUnit> &sunits) {
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SUnits = &sunits;
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// Add pseudo dependency edges for two-address nodes.
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AddPseudoTwoAddrDeps();
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// Calculate node priorities.
|
|
CalculatePriorities();
|
|
}
|
|
|
|
void releaseState() {
|
|
SUnits = 0;
|
|
SethiUllmanNumbers.clear();
|
|
}
|
|
|
|
int getSethiUllmanNumber(unsigned NodeNum) const {
|
|
assert(NodeNum < SethiUllmanNumbers.size());
|
|
return SethiUllmanNumbers[NodeNum];
|
|
}
|
|
|
|
private:
|
|
void AddPseudoTwoAddrDeps();
|
|
void CalculatePriorities();
|
|
int CalcNodePriority(const SUnit *SU);
|
|
};
|
|
|
|
|
|
template<class SF>
|
|
class TDRegReductionPriorityQueue : public RegReductionPriorityQueue<SF> {
|
|
// SUnits - The SUnits for the current graph.
|
|
const std::vector<SUnit> *SUnits;
|
|
|
|
// SethiUllmanNumbers - The SethiUllman number for each node.
|
|
std::vector<int> SethiUllmanNumbers;
|
|
|
|
public:
|
|
TDRegReductionPriorityQueue() {}
|
|
|
|
void initNodes(std::vector<SUnit> &sunits) {
|
|
SUnits = &sunits;
|
|
// Calculate node priorities.
|
|
CalculatePriorities();
|
|
}
|
|
|
|
void releaseState() {
|
|
SUnits = 0;
|
|
SethiUllmanNumbers.clear();
|
|
}
|
|
|
|
int getSethiUllmanNumber(unsigned NodeNum) const {
|
|
assert(NodeNum < SethiUllmanNumbers.size());
|
|
return SethiUllmanNumbers[NodeNum];
|
|
}
|
|
|
|
private:
|
|
void CalculatePriorities();
|
|
int CalcNodePriority(const SUnit *SU);
|
|
};
|
|
}
|
|
|
|
static bool isFloater(const SUnit *SU) {
|
|
if (SU->Node->isTargetOpcode()) {
|
|
if (SU->NumPreds == 0)
|
|
return true;
|
|
if (SU->NumPreds == 1) {
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue;
|
|
|
|
SUnit *PredSU = I->first;
|
|
unsigned Opc = PredSU->Node->getOpcode();
|
|
if (Opc != ISD::EntryToken && Opc != ISD::TokenFactor &&
|
|
Opc != ISD::CopyFromReg && Opc != ISD::CopyToReg)
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static bool isSimpleFloaterUse(const SUnit *SU) {
|
|
unsigned NumOps = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue;
|
|
if (++NumOps > 1)
|
|
return false;
|
|
if (!isFloater(I->first))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// Bottom up
|
|
bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
|
unsigned LeftNum = left->NodeNum;
|
|
unsigned RightNum = right->NodeNum;
|
|
bool LIsTarget = left->Node->isTargetOpcode();
|
|
bool RIsTarget = right->Node->isTargetOpcode();
|
|
int LPriority = SPQ->getSethiUllmanNumber(LeftNum);
|
|
int RPriority = SPQ->getSethiUllmanNumber(RightNum);
|
|
int LBonus = 0;
|
|
int RBonus = 0;
|
|
|
|
// Schedule floaters (e.g. load from some constant address) and those nodes
|
|
// with a single predecessor each first. They maintain / reduce register
|
|
// pressure.
|
|
if (isFloater(left) || isSimpleFloaterUse(left))
|
|
LBonus += 2;
|
|
if (isFloater(right) || isSimpleFloaterUse(right))
|
|
RBonus += 2;
|
|
|
|
// Special tie breaker: if two nodes share a operand, the one that use it
|
|
// as a def&use operand is preferred.
|
|
if (LIsTarget && RIsTarget) {
|
|
if (left->isTwoAddress && !right->isTwoAddress) {
|
|
SDNode *DUNode = left->Node->getOperand(0).Val;
|
|
if (DUNode->isOperand(right->Node))
|
|
LBonus += 2;
|
|
}
|
|
if (!left->isTwoAddress && right->isTwoAddress) {
|
|
SDNode *DUNode = right->Node->getOperand(0).Val;
|
|
if (DUNode->isOperand(left->Node))
|
|
RBonus += 2;
|
|
}
|
|
}
|
|
|
|
if (LPriority+LBonus < RPriority+RBonus)
|
|
return true;
|
|
else if (LPriority+LBonus == RPriority+RBonus)
|
|
if (left->Height > right->Height)
|
|
return true;
|
|
else if (left->Height == right->Height)
|
|
if (left->Depth < right->Depth)
|
|
return true;
|
|
else if (left->Depth == right->Depth)
|
|
if (left->CycleBound > right->CycleBound)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
static inline bool isCopyFromLiveIn(const SUnit *SU) {
|
|
SDNode *N = SU->Node;
|
|
return N->getOpcode() == ISD::CopyFromReg &&
|
|
N->getOperand(N->getNumOperands()-1).getValueType() != MVT::Flag;
|
|
}
|
|
|
|
// FIXME: This is probably too slow!
|
|
static void isReachable(SUnit *SU, SUnit *TargetSU,
|
|
std::set<SUnit *> &Visited, bool &Reached) {
|
|
if (Reached) return;
|
|
if (SU == TargetSU) {
|
|
Reached = true;
|
|
return;
|
|
}
|
|
if (!Visited.insert(SU).second) return;
|
|
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); I != E;
|
|
++I)
|
|
isReachable(I->first, TargetSU, Visited, Reached);
|
|
}
|
|
|
|
static bool isReachable(SUnit *SU, SUnit *TargetSU) {
|
|
std::set<SUnit *> Visited;
|
|
bool Reached = false;
|
|
isReachable(SU, TargetSU, Visited, Reached);
|
|
return Reached;
|
|
}
|
|
|
|
static SUnit *getDefUsePredecessor(SUnit *SU) {
|
|
SDNode *DU = SU->Node->getOperand(0).Val;
|
|
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue; // ignore chain preds
|
|
SUnit *PredSU = I->first;
|
|
if (PredSU->Node == DU)
|
|
return PredSU;
|
|
}
|
|
|
|
// Must be flagged.
|
|
return NULL;
|
|
}
|
|
|
|
static bool canClobber(SUnit *SU, SUnit *Op) {
|
|
if (SU->isTwoAddress)
|
|
return Op == getDefUsePredecessor(SU);
|
|
return false;
|
|
}
|
|
|
|
/// AddPseudoTwoAddrDeps - If two nodes share an operand and one of them uses
|
|
/// it as a def&use operand. Add a pseudo control edge from it to the other
|
|
/// node (if it won't create a cycle) so the two-address one will be scheduled
|
|
/// first (lower in the schedule).
|
|
template<class SF>
|
|
void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i) {
|
|
SUnit *SU = (SUnit *)&((*SUnits)[i]);
|
|
SDNode *Node = SU->Node;
|
|
if (!Node->isTargetOpcode())
|
|
continue;
|
|
|
|
if (SU->isTwoAddress) {
|
|
SUnit *DUSU = getDefUsePredecessor(SU);
|
|
if (!DUSU) continue;
|
|
|
|
for (SUnit::succ_iterator I = DUSU->Succs.begin(), E = DUSU->Succs.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue;
|
|
SUnit *SuccSU = I->first;
|
|
if (SuccSU != SU &&
|
|
(!canClobber(SuccSU, DUSU) ||
|
|
(!SU->isCommutable && SuccSU->isCommutable))){
|
|
if (SuccSU->Depth == SU->Depth && !isReachable(SuccSU, SU)) {
|
|
DEBUG(std::cerr << "Adding an edge from SU # " << SU->NodeNum
|
|
<< " to SU #" << SuccSU->NodeNum << "\n");
|
|
if (SU->addPred(SuccSU, true))
|
|
SU->NumChainPredsLeft++;
|
|
if (SuccSU->addSucc(SU, true))
|
|
SuccSU->NumChainSuccsLeft++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// CalcNodePriority - Priority is the Sethi Ullman number.
|
|
/// Smaller number is the higher priority.
|
|
template<class SF>
|
|
int BURegReductionPriorityQueue<SF>::CalcNodePriority(const SUnit *SU) {
|
|
int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
|
|
if (SethiUllmanNumber != 0)
|
|
return SethiUllmanNumber;
|
|
|
|
unsigned Opc = SU->Node->getOpcode();
|
|
if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
|
|
SethiUllmanNumber = INT_MAX - 10;
|
|
else if (SU->NumSuccsLeft == 0)
|
|
// If SU does not have a use, i.e. it doesn't produce a value that would
|
|
// be consumed (e.g. store), then it terminates a chain of computation.
|
|
// Give it a small SethiUllman number so it will be scheduled right before its
|
|
// predecessors that it doesn't lengthen their live ranges.
|
|
SethiUllmanNumber = INT_MIN + 10;
|
|
// FIXME: remove this else if? It seems to reduce register spills but often
|
|
// ends up increasing runtime. Need to investigate.
|
|
else if (SU->NumPredsLeft == 0 &&
|
|
(Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
|
|
SethiUllmanNumber = INT_MAX - 10;
|
|
else {
|
|
int Extra = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue; // ignore chain preds
|
|
SUnit *PredSU = I->first;
|
|
int PredSethiUllman = CalcNodePriority(PredSU);
|
|
if (PredSethiUllman > SethiUllmanNumber) {
|
|
SethiUllmanNumber = PredSethiUllman;
|
|
Extra = 0;
|
|
} else if (PredSethiUllman == SethiUllmanNumber && !I->second)
|
|
Extra++;
|
|
}
|
|
|
|
SethiUllmanNumber += Extra;
|
|
}
|
|
|
|
return SethiUllmanNumber;
|
|
}
|
|
|
|
/// CalculatePriorities - Calculate priorities of all scheduling units.
|
|
template<class SF>
|
|
void BURegReductionPriorityQueue<SF>::CalculatePriorities() {
|
|
SethiUllmanNumbers.assign(SUnits->size(), 0);
|
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
|
|
CalcNodePriority(&(*SUnits)[i]);
|
|
}
|
|
|
|
static unsigned SumOfUnscheduledPredsOfSuccs(const SUnit *SU) {
|
|
unsigned Sum = 0;
|
|
for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
|
I != E; ++I) {
|
|
SUnit *SuccSU = I->first;
|
|
for (SUnit::const_pred_iterator II = SuccSU->Preds.begin(),
|
|
EE = SuccSU->Preds.end(); II != EE; ++II) {
|
|
SUnit *PredSU = II->first;
|
|
if (!PredSU->isScheduled)
|
|
Sum++;
|
|
}
|
|
}
|
|
|
|
return Sum;
|
|
}
|
|
|
|
|
|
// Top down
|
|
bool td_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
|
|
unsigned LeftNum = left->NodeNum;
|
|
unsigned RightNum = right->NodeNum;
|
|
int LPriority = SPQ->getSethiUllmanNumber(LeftNum);
|
|
int RPriority = SPQ->getSethiUllmanNumber(RightNum);
|
|
bool LIsTarget = left->Node->isTargetOpcode();
|
|
bool RIsTarget = right->Node->isTargetOpcode();
|
|
bool LIsFloater = LIsTarget && left->NumPreds == 0;
|
|
bool RIsFloater = RIsTarget && right->NumPreds == 0;
|
|
unsigned LBonus = (SumOfUnscheduledPredsOfSuccs(left) == 1) ? 2 : 0;
|
|
unsigned RBonus = (SumOfUnscheduledPredsOfSuccs(right) == 1) ? 2 : 0;
|
|
|
|
if (left->NumSuccs == 0 && right->NumSuccs != 0)
|
|
return false;
|
|
else if (left->NumSuccs != 0 && right->NumSuccs == 0)
|
|
return true;
|
|
|
|
// Special tie breaker: if two nodes share a operand, the one that use it
|
|
// as a def&use operand is preferred.
|
|
if (LIsTarget && RIsTarget) {
|
|
if (left->isTwoAddress && !right->isTwoAddress) {
|
|
SDNode *DUNode = left->Node->getOperand(0).Val;
|
|
if (DUNode->isOperand(right->Node))
|
|
RBonus += 2;
|
|
}
|
|
if (!left->isTwoAddress && right->isTwoAddress) {
|
|
SDNode *DUNode = right->Node->getOperand(0).Val;
|
|
if (DUNode->isOperand(left->Node))
|
|
LBonus += 2;
|
|
}
|
|
}
|
|
if (LIsFloater)
|
|
LBonus -= 2;
|
|
if (RIsFloater)
|
|
RBonus -= 2;
|
|
if (left->NumSuccs == 1)
|
|
LBonus += 2;
|
|
if (right->NumSuccs == 1)
|
|
RBonus += 2;
|
|
|
|
if (LPriority+LBonus < RPriority+RBonus)
|
|
return true;
|
|
else if (LPriority == RPriority)
|
|
if (left->Depth < right->Depth)
|
|
return true;
|
|
else if (left->Depth == right->Depth)
|
|
if (left->NumSuccsLeft > right->NumSuccsLeft)
|
|
return true;
|
|
else if (left->NumSuccsLeft == right->NumSuccsLeft)
|
|
if (left->CycleBound > right->CycleBound)
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
/// CalcNodePriority - Priority is the Sethi Ullman number.
|
|
/// Smaller number is the higher priority.
|
|
template<class SF>
|
|
int TDRegReductionPriorityQueue<SF>::CalcNodePriority(const SUnit *SU) {
|
|
int &SethiUllmanNumber = SethiUllmanNumbers[SU->NodeNum];
|
|
if (SethiUllmanNumber != 0)
|
|
return SethiUllmanNumber;
|
|
|
|
unsigned Opc = SU->Node->getOpcode();
|
|
if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
|
|
SethiUllmanNumber = INT_MAX - 10;
|
|
else if (SU->NumSuccsLeft == 0)
|
|
// If SU does not have a use, i.e. it doesn't produce a value that would
|
|
// be consumed (e.g. store), then it terminates a chain of computation.
|
|
// Give it a small SethiUllman number so it will be scheduled right before its
|
|
// predecessors that it doesn't lengthen their live ranges.
|
|
SethiUllmanNumber = INT_MIN + 10;
|
|
else if (SU->NumPredsLeft == 0 &&
|
|
(Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
|
|
SethiUllmanNumber = 1;
|
|
else {
|
|
int Extra = 0;
|
|
for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
|
|
I != E; ++I) {
|
|
if (I->second) continue; // ignore chain preds
|
|
SUnit *PredSU = I->first;
|
|
int PredSethiUllman = CalcNodePriority(PredSU);
|
|
if (PredSethiUllman > SethiUllmanNumber) {
|
|
SethiUllmanNumber = PredSethiUllman;
|
|
Extra = 0;
|
|
} else if (PredSethiUllman == SethiUllmanNumber && !I->second)
|
|
Extra++;
|
|
}
|
|
|
|
SethiUllmanNumber += Extra;
|
|
}
|
|
|
|
return SethiUllmanNumber;
|
|
}
|
|
|
|
/// CalculatePriorities - Calculate priorities of all scheduling units.
|
|
template<class SF>
|
|
void TDRegReductionPriorityQueue<SF>::CalculatePriorities() {
|
|
SethiUllmanNumbers.assign(SUnits->size(), 0);
|
|
|
|
for (unsigned i = 0, e = SUnits->size(); i != e; ++i)
|
|
CalcNodePriority(&(*SUnits)[i]);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Public Constructor Functions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
|
|
SelectionDAG *DAG,
|
|
MachineBasicBlock *BB) {
|
|
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
|
|
new BURegReductionPriorityQueue<bu_ls_rr_sort>());
|
|
}
|
|
|
|
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
|
|
SelectionDAG *DAG,
|
|
MachineBasicBlock *BB) {
|
|
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
|
|
new TDRegReductionPriorityQueue<td_ls_rr_sort>());
|
|
}
|
|
|