Jyotsna Verma 810848d5b3 Hexagon: Replace switch-case in isDotNewInst with TSFlags. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178281 91177308-0d34-0410-b5e6-96231b3b80d8

2013-03-28 19:44:04 +00:00

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InstPrinter

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MCTargetDesc

Hexagon: Enable SupportDebugInfomation and DwarfInSection flags.

2013-03-28 19:34:49 +00:00

TargetInfo

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CMakeLists.txt

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Hexagon.h

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Hexagon.td

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HexagonAsmPrinter.cpp

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HexagonAsmPrinter.h

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HexagonCallingConv.td

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HexagonCallingConvLower.cpp

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HexagonCallingConvLower.h

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HexagonCFGOptimizer.cpp

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HexagonExpandPredSpillCode.cpp

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HexagonFixupHwLoops.cpp

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HexagonFrameLowering.cpp

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HexagonFrameLowering.h

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HexagonHardwareLoops.cpp

Switch to LLVM support function abs64 to keep VS2008 happy.

2013-03-27 13:15:08 +00:00

HexagonInstrFormats.td

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HexagonInstrFormatsV4.td

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HexagonInstrInfo.cpp

Hexagon: Replace switch-case in isDotNewInst with TSFlags.

2013-03-28 19:44:04 +00:00

HexagonInstrInfo.h

Hexagon: Replace switch-case in isDotNewInst with TSFlags.

2013-03-28 19:44:04 +00:00

HexagonInstrInfo.td

Hexagon: Replace switch-case in isDotNewInst with TSFlags.

2013-03-28 19:44:04 +00:00

HexagonInstrInfoV3.td

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HexagonInstrInfoV4.td

Hexagon: Use multiclass for gp-relative instructions.

2013-03-28 16:25:57 +00:00

HexagonInstrInfoV5.td

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HexagonIntrinsics.td

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HexagonIntrinsicsDerived.td

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HexagonIntrinsicsV3.td

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HexagonIntrinsicsV4.td

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HexagonIntrinsicsV5.td

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HexagonISelDAGToDAG.cpp

Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.

2013-03-22 18:41:34 +00:00

HexagonISelLowering.cpp

DAGCombiner: Use correct value type for checking legality of BR_CC v3

2013-03-08 15:36:57 +00:00

HexagonISelLowering.h

Hexagon: Add support to lower block address.

2013-03-07 19:10:28 +00:00

HexagonMachineFunctionInfo.h

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HexagonMachineScheduler.cpp

Cleanup #includes.

2013-03-10 13:11:23 +00:00

HexagonMachineScheduler.h

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HexagonMCInstLower.cpp

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HexagonNewValueJump.cpp

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HexagonOperands.td

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HexagonPeephole.cpp

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HexagonRegisterInfo.cpp

Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.

2013-03-22 18:41:34 +00:00

HexagonRegisterInfo.h

Remove code copied from GenRegisterInfo.inc.

2013-02-22 01:15:08 +00:00

HexagonRegisterInfo.td

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HexagonRemoveSZExtArgs.cpp

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HexagonSchedule.td

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HexagonScheduleV4.td

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HexagonSelectCCInfo.td

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HexagonSelectionDAGInfo.cpp

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HexagonSelectionDAGInfo.h

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HexagonSplitTFRCondSets.cpp

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HexagonSubtarget.cpp

Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.

2013-03-22 18:41:34 +00:00

HexagonSubtarget.h

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HexagonTargetMachine.cpp

Hexagon: Disable optimizations at O0.

2013-03-27 11:14:24 +00:00

HexagonTargetMachine.h

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HexagonTargetObjectFile.cpp

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HexagonTargetObjectFile.h

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HexagonVarargsCallingConvention.h

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HexagonVLIWPacketizer.cpp

Hexagon: Replace switch-case in isDotNewInst with TSFlags.

2013-03-28 19:44:04 +00:00

LLVMBuild.txt

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Makefile

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