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llvm-6502/include/llvm/Target
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Evan Cheng 1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
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Mangler.h
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SubtargetFeature.h
The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a
2010-05-11 00:30:02 +00:00
Target.td
tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
2010-05-20 20:20:32 +00:00
TargetAsmBackend.h
MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can
2010-05-12 00:38:17 +00:00
TargetAsmLexer.h
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TargetAsmParser.h
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TargetCallingConv.td
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TargetData.h
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TargetELFWriterInfo.h
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TargetFrameInfo.h
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TargetInstrDesc.h
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TargetInstrInfo.h
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
2010-05-06 20:33:48 +00:00
TargetInstrItineraries.h
Initial support for different kinds of FU reservation.
2010-04-07 18:19:32 +00:00
TargetIntrinsicInfo.h
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TargetJITInfo.h
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TargetLowering.h
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
2010-05-20 23:26:43 +00:00
TargetLoweringObjectFile.h
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TargetMachine.h
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
2010-05-20 23:26:43 +00:00
TargetOpcodes.h
Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
2010-05-01 00:28:44 +00:00
TargetOptions.h
Remove the -enable-sjlj-eh option, which doesn't do anything.
2010-05-02 15:36:26 +00:00
TargetRegisterInfo.h
Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
2010-05-14 23:21:14 +00:00
TargetRegistry.h
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TargetSchedule.td
Make processor FUs unique for given itinerary. This extends the limit of 32
2010-04-18 20:31:01 +00:00
TargetSelect.h
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TargetSelectionDAG.td
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TargetSelectionDAGInfo.h
Fix a comment.
2010-05-11 18:03:41 +00:00
TargetSubtarget.h
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