Scott Michel 79698f60c4 Add more patterns to match in the integer comparison test harnesses. ...

Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48575 91177308-0d34-0410-b5e6-96231b3b80d8

2008-03-20 00:51:36 +00:00

..

and_ops.ll

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call_indirect.ll

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2008-03-05 23:00:19 +00:00

call.ll

remove extraneous &&'s from tests, as Scott is apparently not going to.

2008-01-18 19:53:43 +00:00

ctpop.ll

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2008-03-05 23:00:19 +00:00

dg.exp

Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll

2007-12-19 20:15:47 +00:00

dp_farith.ll

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2008-03-05 23:00:19 +00:00

eqv.ll

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2008-03-05 23:00:19 +00:00

extract_elt.ll

Overhaul Cell SPU's addressing mode internals so that there are now

2008-01-29 02:16:57 +00:00

fcmp.ll

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2008-03-05 23:00:19 +00:00

fdiv.ll

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fneg-fabs.ll

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icmp8.ll

Add more patterns to match in the integer comparison test harnesses.

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icmp16.ll

Add more patterns to match in the integer comparison test harnesses.

2008-03-20 00:51:36 +00:00

icmp32.ll

Add more patterns to match in the integer comparison test harnesses.

2008-03-20 00:51:36 +00:00

immed16.ll

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immed32.ll

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2008-03-05 23:00:19 +00:00

immed64.ll

Refine Cell's i64 constant generation code to cover more constants where the

2008-03-06 04:02:54 +00:00

int2fp.ll

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2008-03-05 23:00:19 +00:00

intrinsics_branch.ll

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intrinsics_float.ll

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intrinsics_logical.ll

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mul_ops.ll

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2008-03-05 23:00:19 +00:00

nand.ll

More CellSPU refinement and progress:

2008-01-11 02:53:15 +00:00

or_ops.ll

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2008-03-05 23:00:19 +00:00

rotate_ops.ll

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select_bits.ll

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shift_ops.ll

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sp_farith.ll

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struct_1.ll

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vec_const.ll

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vecinsert.ll

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2008-03-05 23:00:19 +00:00