Roman Divacky 1d6d49fbb1 SparcV9 doesnt have rem instruction either. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193789 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-31 19:22:33 +00:00

..

AArch64

[AArch64] Make the use of FP instructions optional, but enabled by default.

2013-10-31 09:32:11 +00:00

ARM

Convert another llc -filetype=obj test.

2013-10-28 21:12:15 +00:00

CPP

[tests] Cleanup initialization of test suffixes.

2013-08-16 00:37:11 +00:00

Generic

Change objectsize intrinsic to accept different address spaces.

2013-10-07 18:06:48 +00:00

Hexagon

TBAA: remove !tbaa from testing cases when they are not needed.

2013-09-30 18:17:35 +00:00

Inputs

Debug Info: add an identifier field to DICompositeType.

2013-08-26 22:39:55 +00:00

Mips

[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests

2013-10-30 15:45:42 +00:00

MSP430

Make sure SP is always aligned on a 2 byte boundary

2013-10-24 09:32:31 +00:00

NVPTX

[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc

2013-10-11 12:39:39 +00:00

PowerPC

Convert another llc -filetype=obj test.

2013-10-28 22:17:19 +00:00

R600

Fix CodeGen for unaligned loads with address spaces

2013-10-30 23:30:05 +00:00

SPARC

SparcV9 doesnt have rem instruction either.

2013-10-31 19:22:33 +00:00

SystemZ

[SystemZ] Automatically detect zEC12 and z196 hosts

2013-10-31 12:14:17 +00:00

Thumb

17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets

2013-10-17 19:52:05 +00:00

Thumb2

MachineSink: Fix and tweak critical-edge breaking heuristic.

2013-10-14 16:57:17 +00:00

X86

Merge and filecheckize.

2013-10-31 17:50:45 +00:00

XCore

XCore target fix bug in emitArrayBound() causing segmentation fault

2013-10-11 10:27:13 +00:00