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cf0db29df2
The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240137 91177308-0d34-0410-b5e6-96231b3b80d8
498 lines
18 KiB
C++
498 lines
18 KiB
C++
//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the Sparc Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcRegisterInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "sparc-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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/// A disassembler class for Sparc.
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class SparcDisassembler : public MCDisassembler {
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public:
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SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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virtual ~SparcDisassembler() {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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} // namespace
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namespace llvm {
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extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget;
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}
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static MCDisassembler *createSparcDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new SparcDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeSparcDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(TheSparcTarget,
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createSparcDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheSparcV9Target,
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createSparcDisassembler);
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TargetRegistry::RegisterMCDisassembler(TheSparcelTarget,
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createSparcDisassembler);
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}
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static const unsigned IntRegDecoderTable[] = {
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SP::G0, SP::G1, SP::G2, SP::G3,
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SP::G4, SP::G5, SP::G6, SP::G7,
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SP::O0, SP::O1, SP::O2, SP::O3,
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SP::O4, SP::O5, SP::O6, SP::O7,
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SP::L0, SP::L1, SP::L2, SP::L3,
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SP::L4, SP::L5, SP::L6, SP::L7,
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SP::I0, SP::I1, SP::I2, SP::I3,
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SP::I4, SP::I5, SP::I6, SP::I7 };
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static const unsigned FPRegDecoderTable[] = {
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SP::F0, SP::F1, SP::F2, SP::F3,
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SP::F4, SP::F5, SP::F6, SP::F7,
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SP::F8, SP::F9, SP::F10, SP::F11,
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SP::F12, SP::F13, SP::F14, SP::F15,
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SP::F16, SP::F17, SP::F18, SP::F19,
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SP::F20, SP::F21, SP::F22, SP::F23,
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SP::F24, SP::F25, SP::F26, SP::F27,
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SP::F28, SP::F29, SP::F30, SP::F31 };
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static const unsigned DFPRegDecoderTable[] = {
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SP::D0, SP::D16, SP::D1, SP::D17,
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SP::D2, SP::D18, SP::D3, SP::D19,
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SP::D4, SP::D20, SP::D5, SP::D21,
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SP::D6, SP::D22, SP::D7, SP::D23,
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SP::D8, SP::D24, SP::D9, SP::D25,
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SP::D10, SP::D26, SP::D11, SP::D27,
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SP::D12, SP::D28, SP::D13, SP::D29,
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SP::D14, SP::D30, SP::D15, SP::D31 };
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static const unsigned QFPRegDecoderTable[] = {
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SP::Q0, SP::Q8, ~0U, ~0U,
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SP::Q1, SP::Q9, ~0U, ~0U,
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SP::Q2, SP::Q10, ~0U, ~0U,
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SP::Q3, SP::Q11, ~0U, ~0U,
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SP::Q4, SP::Q12, ~0U, ~0U,
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SP::Q5, SP::Q13, ~0U, ~0U,
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SP::Q6, SP::Q14, ~0U, ~0U,
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SP::Q7, SP::Q15, ~0U, ~0U } ;
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static const unsigned FCCRegDecoderTable[] = {
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SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
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static const unsigned ASRRegDecoderTable[] = {
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SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
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SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
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SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
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SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
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SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
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SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
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SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
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SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
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static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = IntRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = FPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = DFPRegDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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unsigned Reg = QFPRegDecoderTable[RegNo];
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if (Reg == ~0U)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 3)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 31)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder);
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#include "SparcGenDisassemblerTables.inc"
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/// Read four bytes from the ArrayRef and return 32 bit word.
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static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn,
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bool IsLittleEndian) {
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// We want to read exactly 4 Bytes of data.
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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Insn = IsLittleEndian
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? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
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(Bytes[3] << 24)
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: (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
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(Bytes[0] << 24);
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return MCDisassembler::Success;
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}
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DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const {
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uint32_t Insn;
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bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
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DecodeStatus Result =
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readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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// Calling the auto-generated decoder function.
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Result =
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decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
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if (Result != MCDisassembler::Fail) {
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Size = 4;
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return Result;
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}
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return MCDisassembler::Fail;
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}
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typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder,
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bool isLoad, DecodeFunc DecodeRD) {
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unsigned rd = fieldFromInstruction(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction(insn, 14, 5);
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bool isImm = fieldFromInstruction(insn, 13, 1);
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bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
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unsigned asi = fieldFromInstruction(insn, 5, 8);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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else
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rs2 = fieldFromInstruction(insn, 0, 5);
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DecodeStatus status;
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if (isLoad) {
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status = DecodeRD(MI, rd, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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// Decode rs1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode imm|rs2.
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if (isImm)
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MI.addOperand(MCOperand::createImm(simm13));
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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if (hasAsi)
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MI.addOperand(MCOperand::createImm(asi));
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if (!isLoad) {
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status = DecodeRD(MI, rd, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeIntRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeFPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeDFPRegsRegisterClass);
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}
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static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, true,
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DecodeQFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeIntRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
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const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeDFPRegsRegisterClass);
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}
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static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
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uint64_t Address, const void *Decoder) {
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return DecodeMem(Inst, insn, Address, Decoder, false,
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DecodeQFPRegsRegisterClass);
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t Width, MCInst &MI,
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const void *Decoder) {
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const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
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return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
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Offset, Width);
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}
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static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
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uint64_t Address, const void *Decoder) {
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unsigned tgt = fieldFromInstruction(insn, 0, 30);
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tgt <<= 2;
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if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
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0, 30, MI, Decoder))
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MI.addOperand(MCOperand::createImm(tgt));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
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uint64_t Address, const void *Decoder) {
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unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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MI.addOperand(MCOperand::createImm(tgt));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder) {
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unsigned rd = fieldFromInstruction(insn, 25, 5);
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unsigned rs1 = fieldFromInstruction(insn, 14, 5);
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unsigned isImm = fieldFromInstruction(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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else
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rs2 = fieldFromInstruction(insn, 0, 5);
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// Decode RD.
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DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode RS1.
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status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode RS1 | SIMM13.
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if (isImm)
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MI.addOperand(MCOperand::createImm(simm13));
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else {
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status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
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const void *Decoder) {
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unsigned rs1 = fieldFromInstruction(insn, 14, 5);
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unsigned isImm = fieldFromInstruction(insn, 13, 1);
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unsigned rs2 = 0;
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unsigned simm13 = 0;
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if (isImm)
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simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
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else
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rs2 = fieldFromInstruction(insn, 0, 5);
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// Decode RS1.
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DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
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if (status != MCDisassembler::Success)
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return status;
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// Decode RS2 | SIMM13.
|
|
if (isImm)
|
|
MI.addOperand(MCOperand::createImm(simm13));
|
|
else {
|
|
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
|
|
if (status != MCDisassembler::Success)
|
|
return status;
|
|
}
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
|
|
const void *Decoder) {
|
|
|
|
unsigned rd = fieldFromInstruction(insn, 25, 5);
|
|
unsigned rs1 = fieldFromInstruction(insn, 14, 5);
|
|
unsigned isImm = fieldFromInstruction(insn, 13, 1);
|
|
bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
|
|
unsigned asi = fieldFromInstruction(insn, 5, 8);
|
|
unsigned rs2 = 0;
|
|
unsigned simm13 = 0;
|
|
if (isImm)
|
|
simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
|
|
else
|
|
rs2 = fieldFromInstruction(insn, 0, 5);
|
|
|
|
// Decode RD.
|
|
DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
|
|
if (status != MCDisassembler::Success)
|
|
return status;
|
|
|
|
// Decode RS1.
|
|
status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
|
|
if (status != MCDisassembler::Success)
|
|
return status;
|
|
|
|
// Decode RS1 | SIMM13.
|
|
if (isImm)
|
|
MI.addOperand(MCOperand::createImm(simm13));
|
|
else {
|
|
status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
|
|
if (status != MCDisassembler::Success)
|
|
return status;
|
|
}
|
|
|
|
if (hasAsi)
|
|
MI.addOperand(MCOperand::createImm(asi));
|
|
|
|
return MCDisassembler::Success;
|
|
}
|