mirror of
https://github.com/c64scene-ar/llvm-6502.git
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831e0374a7
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33879 91177308-0d34-0410-b5e6-96231b3b80d8
1157 lines
36 KiB
C++
1157 lines
36 KiB
C++
//===-- ScheduleDAGSimple.cpp - Implement a trivial DAG scheduler ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by James M. Laskey and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SchedulerRegistry.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Compiler.h"
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#include <algorithm>
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using namespace llvm;
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namespace {
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static RegisterScheduler
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bfsDAGScheduler("none", " No scheduling: breadth first sequencing",
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createBFS_DAGScheduler);
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static RegisterScheduler
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simpleDAGScheduler("simple",
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" Simple two pass scheduling: minimize critical path "
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"and maximize processor utilization",
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createSimpleDAGScheduler);
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static RegisterScheduler
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noitinDAGScheduler("simple-noitin",
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" Simple two pass scheduling: Same as simple "
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"except using generic latency",
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createNoItinsDAGScheduler);
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class NodeInfo;
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typedef NodeInfo *NodeInfoPtr;
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typedef std::vector<NodeInfoPtr> NIVector;
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typedef std::vector<NodeInfoPtr>::iterator NIIterator;
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//===--------------------------------------------------------------------===//
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///
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/// Node group - This struct is used to manage flagged node groups.
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///
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class NodeGroup {
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public:
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NodeGroup *Next;
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private:
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NIVector Members; // Group member nodes
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NodeInfo *Dominator; // Node with highest latency
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unsigned Latency; // Total latency of the group
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int Pending; // Number of visits pending before
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// adding to order
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public:
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// Ctor.
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NodeGroup() : Next(NULL), Dominator(NULL), Pending(0) {}
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// Accessors
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inline void setDominator(NodeInfo *D) { Dominator = D; }
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inline NodeInfo *getTop() { return Members.front(); }
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inline NodeInfo *getBottom() { return Members.back(); }
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inline NodeInfo *getDominator() { return Dominator; }
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inline void setLatency(unsigned L) { Latency = L; }
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inline unsigned getLatency() { return Latency; }
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inline int getPending() const { return Pending; }
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inline void setPending(int P) { Pending = P; }
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inline int addPending(int I) { return Pending += I; }
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// Pass thru
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inline bool group_empty() { return Members.empty(); }
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inline NIIterator group_begin() { return Members.begin(); }
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inline NIIterator group_end() { return Members.end(); }
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inline void group_push_back(const NodeInfoPtr &NI) {
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Members.push_back(NI);
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}
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inline NIIterator group_insert(NIIterator Pos, const NodeInfoPtr &NI) {
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return Members.insert(Pos, NI);
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}
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inline void group_insert(NIIterator Pos, NIIterator First,
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NIIterator Last) {
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Members.insert(Pos, First, Last);
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}
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static void Add(NodeInfo *D, NodeInfo *U);
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};
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//===--------------------------------------------------------------------===//
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///
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/// NodeInfo - This struct tracks information used to schedule the a node.
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///
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class NodeInfo {
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private:
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int Pending; // Number of visits pending before
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// adding to order
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public:
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SDNode *Node; // DAG node
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InstrStage *StageBegin; // First stage in itinerary
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InstrStage *StageEnd; // Last+1 stage in itinerary
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unsigned Latency; // Total cycles to complete instr
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bool IsCall : 1; // Is function call
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bool IsLoad : 1; // Is memory load
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bool IsStore : 1; // Is memory store
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unsigned Slot; // Node's time slot
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NodeGroup *Group; // Grouping information
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#ifndef NDEBUG
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unsigned Preorder; // Index before scheduling
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#endif
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// Ctor.
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NodeInfo(SDNode *N = NULL)
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: Pending(0)
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, Node(N)
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, StageBegin(NULL)
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, StageEnd(NULL)
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, Latency(0)
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, IsCall(false)
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, Slot(0)
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, Group(NULL)
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#ifndef NDEBUG
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, Preorder(0)
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#endif
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{}
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// Accessors
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inline bool isInGroup() const {
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assert(!Group || !Group->group_empty() && "Group with no members");
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return Group != NULL;
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}
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inline bool isGroupDominator() const {
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return isInGroup() && Group->getDominator() == this;
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}
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inline int getPending() const {
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return Group ? Group->getPending() : Pending;
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}
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inline void setPending(int P) {
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if (Group) Group->setPending(P);
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else Pending = P;
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}
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inline int addPending(int I) {
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if (Group) return Group->addPending(I);
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else return Pending += I;
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}
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};
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//===--------------------------------------------------------------------===//
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///
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/// NodeGroupIterator - Iterates over all the nodes indicated by the node
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/// info. If the node is in a group then iterate over the members of the
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/// group, otherwise just the node info.
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///
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class NodeGroupIterator {
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private:
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NodeInfo *NI; // Node info
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NIIterator NGI; // Node group iterator
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NIIterator NGE; // Node group iterator end
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public:
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// Ctor.
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NodeGroupIterator(NodeInfo *N) : NI(N) {
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// If the node is in a group then set up the group iterator. Otherwise
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// the group iterators will trip first time out.
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if (N->isInGroup()) {
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// get Group
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NodeGroup *Group = NI->Group;
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NGI = Group->group_begin();
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NGE = Group->group_end();
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// Prevent this node from being used (will be in members list
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NI = NULL;
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}
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}
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/// next - Return the next node info, otherwise NULL.
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///
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NodeInfo *next() {
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// If members list
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if (NGI != NGE) return *NGI++;
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// Use node as the result (may be NULL)
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NodeInfo *Result = NI;
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// Only use once
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NI = NULL;
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// Return node or NULL
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return Result;
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}
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};
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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///
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/// NodeGroupOpIterator - Iterates over all the operands of a node. If the
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/// node is a member of a group, this iterates over all the operands of all
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/// the members of the group.
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///
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class NodeGroupOpIterator {
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private:
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NodeInfo *NI; // Node containing operands
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NodeGroupIterator GI; // Node group iterator
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SDNode::op_iterator OI; // Operand iterator
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SDNode::op_iterator OE; // Operand iterator end
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/// CheckNode - Test if node has more operands. If not get the next node
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/// skipping over nodes that have no operands.
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void CheckNode() {
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// Only if operands are exhausted first
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while (OI == OE) {
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// Get next node info
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NodeInfo *NI = GI.next();
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// Exit if nodes are exhausted
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if (!NI) return;
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// Get node itself
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SDNode *Node = NI->Node;
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// Set up the operand iterators
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OI = Node->op_begin();
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OE = Node->op_end();
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}
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}
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public:
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// Ctor.
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NodeGroupOpIterator(NodeInfo *N)
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: NI(N), GI(N), OI(SDNode::op_iterator()), OE(SDNode::op_iterator()) {}
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/// isEnd - Returns true when not more operands are available.
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///
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inline bool isEnd() { CheckNode(); return OI == OE; }
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/// next - Returns the next available operand.
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///
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inline SDOperand next() {
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assert(OI != OE &&
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"Not checking for end of NodeGroupOpIterator correctly");
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return *OI++;
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}
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};
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//===----------------------------------------------------------------------===//
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///
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/// BitsIterator - Provides iteration through individual bits in a bit vector.
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///
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template<class T>
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class BitsIterator {
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private:
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T Bits; // Bits left to iterate through
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public:
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/// Ctor.
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BitsIterator(T Initial) : Bits(Initial) {}
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/// Next - Returns the next bit set or zero if exhausted.
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inline T Next() {
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// Get the rightmost bit set
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T Result = Bits & -Bits;
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// Remove from rest
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Bits &= ~Result;
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// Return single bit or zero
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return Result;
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}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// ResourceTally - Manages the use of resources over time intervals. Each
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/// item (slot) in the tally vector represents the resources used at a given
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/// moment. A bit set to 1 indicates that a resource is in use, otherwise
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/// available. An assumption is made that the tally is large enough to schedule
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/// all current instructions (asserts otherwise.)
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///
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template<class T>
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class ResourceTally {
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private:
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std::vector<T> Tally; // Resources used per slot
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typedef typename std::vector<T>::iterator Iter;
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// Tally iterator
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/// SlotsAvailable - Returns true if all units are available.
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///
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bool SlotsAvailable(Iter Begin, unsigned N, unsigned ResourceSet,
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unsigned &Resource) {
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assert(N && "Must check availability with N != 0");
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// Determine end of interval
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Iter End = Begin + N;
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assert(End <= Tally.end() && "Tally is not large enough for schedule");
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// Iterate thru each resource
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BitsIterator<T> Resources(ResourceSet & ~*Begin);
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while (unsigned Res = Resources.Next()) {
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// Check if resource is available for next N slots
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Iter Interval = End;
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do {
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Interval--;
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if (*Interval & Res) break;
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} while (Interval != Begin);
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// If available for N
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if (Interval == Begin) {
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// Success
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Resource = Res;
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return true;
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}
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}
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// No luck
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Resource = 0;
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return false;
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}
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/// RetrySlot - Finds a good candidate slot to retry search.
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Iter RetrySlot(Iter Begin, unsigned N, unsigned ResourceSet) {
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assert(N && "Must check availability with N != 0");
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// Determine end of interval
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Iter End = Begin + N;
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assert(End <= Tally.end() && "Tally is not large enough for schedule");
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while (Begin != End--) {
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// Clear units in use
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ResourceSet &= ~*End;
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// If no units left then we should go no further
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if (!ResourceSet) return End + 1;
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}
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// Made it all the way through
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return Begin;
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}
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/// FindAndReserveStages - Return true if the stages can be completed. If
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/// so mark as busy.
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bool FindAndReserveStages(Iter Begin,
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InstrStage *Stage, InstrStage *StageEnd) {
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// If at last stage then we're done
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if (Stage == StageEnd) return true;
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// Get number of cycles for current stage
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unsigned N = Stage->Cycles;
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// Check to see if N slots are available, if not fail
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unsigned Resource;
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if (!SlotsAvailable(Begin, N, Stage->Units, Resource)) return false;
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// Check to see if remaining stages are available, if not fail
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if (!FindAndReserveStages(Begin + N, Stage + 1, StageEnd)) return false;
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// Reserve resource
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Reserve(Begin, N, Resource);
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// Success
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return true;
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}
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/// Reserve - Mark busy (set) the specified N slots.
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void Reserve(Iter Begin, unsigned N, unsigned Resource) {
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// Determine end of interval
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Iter End = Begin + N;
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assert(End <= Tally.end() && "Tally is not large enough for schedule");
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// Set resource bit in each slot
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for (; Begin < End; Begin++)
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*Begin |= Resource;
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}
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/// FindSlots - Starting from Begin, locate consecutive slots where all stages
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/// can be completed. Returns the address of first slot.
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Iter FindSlots(Iter Begin, InstrStage *StageBegin, InstrStage *StageEnd) {
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// Track position
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Iter Cursor = Begin;
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// Try all possible slots forward
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while (true) {
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// Try at cursor, if successful return position.
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if (FindAndReserveStages(Cursor, StageBegin, StageEnd)) return Cursor;
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// Locate a better position
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Cursor = RetrySlot(Cursor + 1, StageBegin->Cycles, StageBegin->Units);
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}
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}
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public:
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/// Initialize - Resize and zero the tally to the specified number of time
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/// slots.
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inline void Initialize(unsigned N) {
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Tally.assign(N, 0); // Initialize tally to all zeros.
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}
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// FindAndReserve - Locate an ideal slot for the specified stages and mark
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// as busy.
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unsigned FindAndReserve(unsigned Slot, InstrStage *StageBegin,
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InstrStage *StageEnd) {
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// Where to begin
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Iter Begin = Tally.begin() + Slot;
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// Find a free slot
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Iter Where = FindSlots(Begin, StageBegin, StageEnd);
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// Distance is slot number
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unsigned Final = Where - Tally.begin();
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return Final;
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}
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};
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//===----------------------------------------------------------------------===//
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///
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/// ScheduleDAGSimple - Simple two pass scheduler.
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///
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class VISIBILITY_HIDDEN ScheduleDAGSimple : public ScheduleDAG {
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private:
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bool NoSched; // Just do a BFS schedule, nothing fancy
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bool NoItins; // Don't use itineraries?
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ResourceTally<unsigned> Tally; // Resource usage tally
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unsigned NSlots; // Total latency
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static const unsigned NotFound = ~0U; // Search marker
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unsigned NodeCount; // Number of nodes in DAG
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std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
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bool HasGroups; // True if there are any groups
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NodeInfo *Info; // Info for nodes being scheduled
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NIVector Ordering; // Emit ordering of nodes
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NodeGroup *HeadNG, *TailNG; // Keep track of allocated NodeGroups
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public:
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// Ctor.
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ScheduleDAGSimple(bool noSched, bool noItins, SelectionDAG &dag,
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MachineBasicBlock *bb, const TargetMachine &tm)
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: ScheduleDAG(dag, bb, tm), NoSched(noSched), NoItins(noItins), NSlots(0),
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NodeCount(0), HasGroups(false), Info(NULL), HeadNG(NULL), TailNG(NULL) {
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assert(&TII && "Target doesn't provide instr info?");
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assert(&MRI && "Target doesn't provide register info?");
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}
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virtual ~ScheduleDAGSimple() {
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if (Info)
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delete[] Info;
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NodeGroup *NG = HeadNG;
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while (NG) {
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NodeGroup *NextSU = NG->Next;
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delete NG;
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NG = NextSU;
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}
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}
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void Schedule();
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/// getNI - Returns the node info for the specified node.
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///
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NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
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private:
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static bool isDefiner(NodeInfo *A, NodeInfo *B);
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void IncludeNode(NodeInfo *NI);
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void VisitAll();
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void GatherSchedulingInfo();
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void FakeGroupDominators();
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bool isStrongDependency(NodeInfo *A, NodeInfo *B);
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bool isWeakDependency(NodeInfo *A, NodeInfo *B);
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void ScheduleBackward();
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void ScheduleForward();
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void AddToGroup(NodeInfo *D, NodeInfo *U);
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/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
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///
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void PrepareNodeInfo();
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/// IdentifyGroups - Put flagged nodes into groups.
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///
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void IdentifyGroups();
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/// print - Print ordering to specified output stream.
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///
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void print(std::ostream &O) const;
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void print(std::ostream *O) const { if (O) print(*O); }
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void dump(const char *tag) const;
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virtual void dump() const;
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/// EmitAll - Emit all nodes in schedule sorted order.
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///
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void EmitAll();
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/// printNI - Print node info.
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///
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void printNI(std::ostream &O, NodeInfo *NI) const;
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void printNI(std::ostream *O, NodeInfo *NI) const { if (O) printNI(*O, NI); }
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/// printChanges - Hilight changes in order caused by scheduling.
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///
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void printChanges(unsigned Index) const;
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};
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//===----------------------------------------------------------------------===//
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/// Special case itineraries.
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///
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enum {
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CallLatency = 40, // To push calls back in time
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RSInteger = 0xC0000000, // Two integer units
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RSFloat = 0x30000000, // Two float units
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RSLoadStore = 0x0C000000, // Two load store units
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RSBranch = 0x02000000 // One branch unit
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};
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static InstrStage LoadStage = { 5, RSLoadStore };
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static InstrStage StoreStage = { 2, RSLoadStore };
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static InstrStage IntStage = { 2, RSInteger };
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static InstrStage FloatStage = { 3, RSFloat };
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//===----------------------------------------------------------------------===//
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} // namespace
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//===----------------------------------------------------------------------===//
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/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
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///
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void ScheduleDAGSimple::PrepareNodeInfo() {
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// Allocate node information
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Info = new NodeInfo[NodeCount];
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unsigned i = 0;
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for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
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E = DAG.allnodes_end(); I != E; ++I, ++i) {
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// Fast reference to node schedule info
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NodeInfo* NI = &Info[i];
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// Set up map
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Map[I] = NI;
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// Set node
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NI->Node = I;
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// Set pending visit count
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NI->setPending(I->use_size());
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}
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}
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/// IdentifyGroups - Put flagged nodes into groups.
|
|
///
|
|
void ScheduleDAGSimple::IdentifyGroups() {
|
|
for (unsigned i = 0, N = NodeCount; i < N; i++) {
|
|
NodeInfo* NI = &Info[i];
|
|
SDNode *Node = NI->Node;
|
|
|
|
// For each operand (in reverse to only look at flags)
|
|
for (unsigned N = Node->getNumOperands(); 0 < N--;) {
|
|
// Get operand
|
|
SDOperand Op = Node->getOperand(N);
|
|
// No more flags to walk
|
|
if (Op.getValueType() != MVT::Flag) break;
|
|
// Add to node group
|
|
AddToGroup(getNI(Op.Val), NI);
|
|
// Let everyone else know
|
|
HasGroups = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// CountInternalUses - Returns the number of edges between the two nodes.
|
|
///
|
|
static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U) {
|
|
unsigned N = 0;
|
|
for (unsigned M = U->Node->getNumOperands(); 0 < M--;) {
|
|
SDOperand Op = U->Node->getOperand(M);
|
|
if (Op.Val == D->Node) N++;
|
|
}
|
|
|
|
return N;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
/// Add - Adds a definer and user pair to a node group.
|
|
///
|
|
void ScheduleDAGSimple::AddToGroup(NodeInfo *D, NodeInfo *U) {
|
|
// Get current groups
|
|
NodeGroup *DGroup = D->Group;
|
|
NodeGroup *UGroup = U->Group;
|
|
// If both are members of groups
|
|
if (DGroup && UGroup) {
|
|
// There may have been another edge connecting
|
|
if (DGroup == UGroup) return;
|
|
// Add the pending users count
|
|
DGroup->addPending(UGroup->getPending());
|
|
// For each member of the users group
|
|
NodeGroupIterator UNGI(U);
|
|
while (NodeInfo *UNI = UNGI.next() ) {
|
|
// Change the group
|
|
UNI->Group = DGroup;
|
|
// For each member of the definers group
|
|
NodeGroupIterator DNGI(D);
|
|
while (NodeInfo *DNI = DNGI.next() ) {
|
|
// Remove internal edges
|
|
DGroup->addPending(-CountInternalUses(DNI, UNI));
|
|
}
|
|
}
|
|
// Merge the two lists
|
|
DGroup->group_insert(DGroup->group_end(),
|
|
UGroup->group_begin(), UGroup->group_end());
|
|
} else if (DGroup) {
|
|
// Make user member of definers group
|
|
U->Group = DGroup;
|
|
// Add users uses to definers group pending
|
|
DGroup->addPending(U->Node->use_size());
|
|
// For each member of the definers group
|
|
NodeGroupIterator DNGI(D);
|
|
while (NodeInfo *DNI = DNGI.next() ) {
|
|
// Remove internal edges
|
|
DGroup->addPending(-CountInternalUses(DNI, U));
|
|
}
|
|
DGroup->group_push_back(U);
|
|
} else if (UGroup) {
|
|
// Make definer member of users group
|
|
D->Group = UGroup;
|
|
// Add definers uses to users group pending
|
|
UGroup->addPending(D->Node->use_size());
|
|
// For each member of the users group
|
|
NodeGroupIterator UNGI(U);
|
|
while (NodeInfo *UNI = UNGI.next() ) {
|
|
// Remove internal edges
|
|
UGroup->addPending(-CountInternalUses(D, UNI));
|
|
}
|
|
UGroup->group_insert(UGroup->group_begin(), D);
|
|
} else {
|
|
D->Group = U->Group = DGroup = new NodeGroup();
|
|
DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
|
|
CountInternalUses(D, U));
|
|
DGroup->group_push_back(D);
|
|
DGroup->group_push_back(U);
|
|
|
|
if (HeadNG == NULL)
|
|
HeadNG = DGroup;
|
|
if (TailNG != NULL)
|
|
TailNG->Next = DGroup;
|
|
TailNG = DGroup;
|
|
}
|
|
}
|
|
|
|
|
|
/// print - Print ordering to specified output stream.
|
|
///
|
|
void ScheduleDAGSimple::print(std::ostream &O) const {
|
|
#ifndef NDEBUG
|
|
O << "Ordering\n";
|
|
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
|
NodeInfo *NI = Ordering[i];
|
|
printNI(O, NI);
|
|
O << "\n";
|
|
if (NI->isGroupDominator()) {
|
|
NodeGroup *Group = NI->Group;
|
|
for (NIIterator NII = Group->group_begin(), E = Group->group_end();
|
|
NII != E; NII++) {
|
|
O << " ";
|
|
printNI(O, *NII);
|
|
O << "\n";
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void ScheduleDAGSimple::dump(const char *tag) const {
|
|
cerr << tag; dump();
|
|
}
|
|
|
|
void ScheduleDAGSimple::dump() const {
|
|
print(cerr);
|
|
}
|
|
|
|
|
|
/// EmitAll - Emit all nodes in schedule sorted order.
|
|
///
|
|
void ScheduleDAGSimple::EmitAll() {
|
|
// If this is the first basic block in the function, and if it has live ins
|
|
// that need to be copied into vregs, emit the copies into the top of the
|
|
// block before emitting the code for the block.
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
if (&MF.front() == BB && MF.livein_begin() != MF.livein_end()) {
|
|
for (MachineFunction::livein_iterator LI = MF.livein_begin(),
|
|
E = MF.livein_end(); LI != E; ++LI)
|
|
if (LI->second)
|
|
MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
|
|
LI->first, RegMap->getRegClass(LI->second));
|
|
}
|
|
|
|
DenseMap<SDNode*, unsigned> VRBaseMap;
|
|
|
|
// For each node in the ordering
|
|
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
|
// Get the scheduling info
|
|
NodeInfo *NI = Ordering[i];
|
|
if (NI->isInGroup()) {
|
|
NodeGroupIterator NGI(Ordering[i]);
|
|
while (NodeInfo *NI = NGI.next()) EmitNode(NI->Node, VRBaseMap);
|
|
} else {
|
|
EmitNode(NI->Node, VRBaseMap);
|
|
}
|
|
}
|
|
}
|
|
|
|
/// isFlagDefiner - Returns true if the node defines a flag result.
|
|
static bool isFlagDefiner(SDNode *A) {
|
|
unsigned N = A->getNumValues();
|
|
return N && A->getValueType(N - 1) == MVT::Flag;
|
|
}
|
|
|
|
/// isFlagUser - Returns true if the node uses a flag result.
|
|
///
|
|
static bool isFlagUser(SDNode *A) {
|
|
unsigned N = A->getNumOperands();
|
|
return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
|
|
}
|
|
|
|
/// printNI - Print node info.
|
|
///
|
|
void ScheduleDAGSimple::printNI(std::ostream &O, NodeInfo *NI) const {
|
|
#ifndef NDEBUG
|
|
SDNode *Node = NI->Node;
|
|
O << " "
|
|
<< std::hex << Node << std::dec
|
|
<< ", Lat=" << NI->Latency
|
|
<< ", Slot=" << NI->Slot
|
|
<< ", ARITY=(" << Node->getNumOperands() << ","
|
|
<< Node->getNumValues() << ")"
|
|
<< " " << Node->getOperationName(&DAG);
|
|
if (isFlagDefiner(Node)) O << "<#";
|
|
if (isFlagUser(Node)) O << ">#";
|
|
#endif
|
|
}
|
|
|
|
/// printChanges - Hilight changes in order caused by scheduling.
|
|
///
|
|
void ScheduleDAGSimple::printChanges(unsigned Index) const {
|
|
#ifndef NDEBUG
|
|
// Get the ordered node count
|
|
unsigned N = Ordering.size();
|
|
// Determine if any changes
|
|
unsigned i = 0;
|
|
for (; i < N; i++) {
|
|
NodeInfo *NI = Ordering[i];
|
|
if (NI->Preorder != i) break;
|
|
}
|
|
|
|
if (i < N) {
|
|
cerr << Index << ". New Ordering\n";
|
|
|
|
for (i = 0; i < N; i++) {
|
|
NodeInfo *NI = Ordering[i];
|
|
cerr << " " << NI->Preorder << ". ";
|
|
printNI(cerr, NI);
|
|
cerr << "\n";
|
|
if (NI->isGroupDominator()) {
|
|
NodeGroup *Group = NI->Group;
|
|
for (NIIterator NII = Group->group_begin(), E = Group->group_end();
|
|
NII != E; NII++) {
|
|
cerr << " ";
|
|
printNI(cerr, *NII);
|
|
cerr << "\n";
|
|
}
|
|
}
|
|
}
|
|
} else {
|
|
cerr << Index << ". No Changes\n";
|
|
}
|
|
#endif
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
/// isDefiner - Return true if node A is a definer for B.
|
|
///
|
|
bool ScheduleDAGSimple::isDefiner(NodeInfo *A, NodeInfo *B) {
|
|
// While there are A nodes
|
|
NodeGroupIterator NII(A);
|
|
while (NodeInfo *NI = NII.next()) {
|
|
// Extract node
|
|
SDNode *Node = NI->Node;
|
|
// While there operands in nodes of B
|
|
NodeGroupOpIterator NGOI(B);
|
|
while (!NGOI.isEnd()) {
|
|
SDOperand Op = NGOI.next();
|
|
// If node from A defines a node in B
|
|
if (Node == Op.Val) return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// IncludeNode - Add node to NodeInfo vector.
|
|
///
|
|
void ScheduleDAGSimple::IncludeNode(NodeInfo *NI) {
|
|
// Get node
|
|
SDNode *Node = NI->Node;
|
|
// Ignore entry node
|
|
if (Node->getOpcode() == ISD::EntryToken) return;
|
|
// Check current count for node
|
|
int Count = NI->getPending();
|
|
// If the node is already in list
|
|
if (Count < 0) return;
|
|
// Decrement count to indicate a visit
|
|
Count--;
|
|
// If count has gone to zero then add node to list
|
|
if (!Count) {
|
|
// Add node
|
|
if (NI->isInGroup()) {
|
|
Ordering.push_back(NI->Group->getDominator());
|
|
} else {
|
|
Ordering.push_back(NI);
|
|
}
|
|
// indicate node has been added
|
|
Count--;
|
|
}
|
|
// Mark as visited with new count
|
|
NI->setPending(Count);
|
|
}
|
|
|
|
/// GatherSchedulingInfo - Get latency and resource information about each node.
|
|
///
|
|
void ScheduleDAGSimple::GatherSchedulingInfo() {
|
|
// Get instruction itineraries for the target
|
|
const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
|
|
|
|
// For each node
|
|
for (unsigned i = 0, N = NodeCount; i < N; i++) {
|
|
// Get node info
|
|
NodeInfo* NI = &Info[i];
|
|
SDNode *Node = NI->Node;
|
|
|
|
// If there are itineraries and it is a machine instruction
|
|
if (InstrItins.isEmpty() || NoItins) {
|
|
// If machine opcode
|
|
if (Node->isTargetOpcode()) {
|
|
// Get return type to guess which processing unit
|
|
MVT::ValueType VT = Node->getValueType(0);
|
|
// Get machine opcode
|
|
MachineOpCode TOpc = Node->getTargetOpcode();
|
|
NI->IsCall = TII->isCall(TOpc);
|
|
NI->IsLoad = TII->isLoad(TOpc);
|
|
NI->IsStore = TII->isStore(TOpc);
|
|
|
|
if (TII->isLoad(TOpc)) NI->StageBegin = &LoadStage;
|
|
else if (TII->isStore(TOpc)) NI->StageBegin = &StoreStage;
|
|
else if (MVT::isInteger(VT)) NI->StageBegin = &IntStage;
|
|
else if (MVT::isFloatingPoint(VT)) NI->StageBegin = &FloatStage;
|
|
if (NI->StageBegin) NI->StageEnd = NI->StageBegin + 1;
|
|
}
|
|
} else if (Node->isTargetOpcode()) {
|
|
// get machine opcode
|
|
MachineOpCode TOpc = Node->getTargetOpcode();
|
|
// Check to see if it is a call
|
|
NI->IsCall = TII->isCall(TOpc);
|
|
// Get itinerary stages for instruction
|
|
unsigned II = TII->getSchedClass(TOpc);
|
|
NI->StageBegin = InstrItins.begin(II);
|
|
NI->StageEnd = InstrItins.end(II);
|
|
}
|
|
|
|
// One slot for the instruction itself
|
|
NI->Latency = 1;
|
|
|
|
// Add long latency for a call to push it back in time
|
|
if (NI->IsCall) NI->Latency += CallLatency;
|
|
|
|
// Sum up all the latencies
|
|
for (InstrStage *Stage = NI->StageBegin, *E = NI->StageEnd;
|
|
Stage != E; Stage++) {
|
|
NI->Latency += Stage->Cycles;
|
|
}
|
|
|
|
// Sum up all the latencies for max tally size
|
|
NSlots += NI->Latency;
|
|
}
|
|
|
|
// Unify metrics if in a group
|
|
if (HasGroups) {
|
|
for (unsigned i = 0, N = NodeCount; i < N; i++) {
|
|
NodeInfo* NI = &Info[i];
|
|
|
|
if (NI->isInGroup()) {
|
|
NodeGroup *Group = NI->Group;
|
|
|
|
if (!Group->getDominator()) {
|
|
NIIterator NGI = Group->group_begin(), NGE = Group->group_end();
|
|
NodeInfo *Dominator = *NGI;
|
|
unsigned Latency = 0;
|
|
|
|
for (NGI++; NGI != NGE; NGI++) {
|
|
NodeInfo* NGNI = *NGI;
|
|
Latency += NGNI->Latency;
|
|
if (Dominator->Latency < NGNI->Latency) Dominator = NGNI;
|
|
}
|
|
|
|
Dominator->Latency = Latency;
|
|
Group->setDominator(Dominator);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// VisitAll - Visit each node breadth-wise to produce an initial ordering.
|
|
/// Note that the ordering in the Nodes vector is reversed.
|
|
void ScheduleDAGSimple::VisitAll() {
|
|
// Add first element to list
|
|
NodeInfo *NI = getNI(DAG.getRoot().Val);
|
|
if (NI->isInGroup()) {
|
|
Ordering.push_back(NI->Group->getDominator());
|
|
} else {
|
|
Ordering.push_back(NI);
|
|
}
|
|
|
|
// Iterate through all nodes that have been added
|
|
for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
|
|
// Visit all operands
|
|
NodeGroupOpIterator NGI(Ordering[i]);
|
|
while (!NGI.isEnd()) {
|
|
// Get next operand
|
|
SDOperand Op = NGI.next();
|
|
// Get node
|
|
SDNode *Node = Op.Val;
|
|
// Ignore passive nodes
|
|
if (isPassiveNode(Node)) continue;
|
|
// Check out node
|
|
IncludeNode(getNI(Node));
|
|
}
|
|
}
|
|
|
|
// Add entry node last (IncludeNode filters entry nodes)
|
|
if (DAG.getEntryNode().Val != DAG.getRoot().Val)
|
|
Ordering.push_back(getNI(DAG.getEntryNode().Val));
|
|
|
|
// Reverse the order
|
|
std::reverse(Ordering.begin(), Ordering.end());
|
|
}
|
|
|
|
/// FakeGroupDominators - Set dominators for non-scheduling.
|
|
///
|
|
void ScheduleDAGSimple::FakeGroupDominators() {
|
|
for (unsigned i = 0, N = NodeCount; i < N; i++) {
|
|
NodeInfo* NI = &Info[i];
|
|
|
|
if (NI->isInGroup()) {
|
|
NodeGroup *Group = NI->Group;
|
|
|
|
if (!Group->getDominator()) {
|
|
Group->setDominator(NI);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// isStrongDependency - Return true if node A has results used by node B.
|
|
/// I.E., B must wait for latency of A.
|
|
bool ScheduleDAGSimple::isStrongDependency(NodeInfo *A, NodeInfo *B) {
|
|
// If A defines for B then it's a strong dependency or
|
|
// if a load follows a store (may be dependent but why take a chance.)
|
|
return isDefiner(A, B) || (A->IsStore && B->IsLoad);
|
|
}
|
|
|
|
/// isWeakDependency Return true if node A produces a result that will
|
|
/// conflict with operands of B. It is assumed that we have called
|
|
/// isStrongDependency prior.
|
|
bool ScheduleDAGSimple::isWeakDependency(NodeInfo *A, NodeInfo *B) {
|
|
// TODO check for conflicting real registers and aliases
|
|
#if 0 // FIXME - Since we are in SSA form and not checking register aliasing
|
|
return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
|
|
#else
|
|
return A->Node->getOpcode() == ISD::EntryToken;
|
|
#endif
|
|
}
|
|
|
|
/// ScheduleBackward - Schedule instructions so that any long latency
|
|
/// instructions and the critical path get pushed back in time. Time is run in
|
|
/// reverse to allow code reuse of the Tally and eliminate the overhead of
|
|
/// biasing every slot indices against NSlots.
|
|
void ScheduleDAGSimple::ScheduleBackward() {
|
|
// Size and clear the resource tally
|
|
Tally.Initialize(NSlots);
|
|
// Get number of nodes to schedule
|
|
unsigned N = Ordering.size();
|
|
|
|
// For each node being scheduled
|
|
for (unsigned i = N; 0 < i--;) {
|
|
NodeInfo *NI = Ordering[i];
|
|
// Track insertion
|
|
unsigned Slot = NotFound;
|
|
|
|
// Compare against those previously scheduled nodes
|
|
unsigned j = i + 1;
|
|
for (; j < N; j++) {
|
|
// Get following instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
|
|
// Check dependency against previously inserted nodes
|
|
if (isStrongDependency(NI, Other)) {
|
|
Slot = Other->Slot + Other->Latency;
|
|
break;
|
|
} else if (isWeakDependency(NI, Other)) {
|
|
Slot = Other->Slot;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If independent of others (or first entry)
|
|
if (Slot == NotFound) Slot = 0;
|
|
|
|
#if 0 // FIXME - measure later
|
|
// Find a slot where the needed resources are available
|
|
if (NI->StageBegin != NI->StageEnd)
|
|
Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
|
|
#endif
|
|
|
|
// Set node slot
|
|
NI->Slot = Slot;
|
|
|
|
// Insert sort based on slot
|
|
j = i + 1;
|
|
for (; j < N; j++) {
|
|
// Get following instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
// Should we look further (remember slots are in reverse time)
|
|
if (Slot >= Other->Slot) break;
|
|
// Shuffle other into ordering
|
|
Ordering[j - 1] = Other;
|
|
}
|
|
// Insert node in proper slot
|
|
if (j != i + 1) Ordering[j - 1] = NI;
|
|
}
|
|
}
|
|
|
|
/// ScheduleForward - Schedule instructions to maximize packing.
|
|
///
|
|
void ScheduleDAGSimple::ScheduleForward() {
|
|
// Size and clear the resource tally
|
|
Tally.Initialize(NSlots);
|
|
// Get number of nodes to schedule
|
|
unsigned N = Ordering.size();
|
|
|
|
// For each node being scheduled
|
|
for (unsigned i = 0; i < N; i++) {
|
|
NodeInfo *NI = Ordering[i];
|
|
// Track insertion
|
|
unsigned Slot = NotFound;
|
|
|
|
// Compare against those previously scheduled nodes
|
|
unsigned j = i;
|
|
for (; 0 < j--;) {
|
|
// Get following instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
|
|
// Check dependency against previously inserted nodes
|
|
if (isStrongDependency(Other, NI)) {
|
|
Slot = Other->Slot + Other->Latency;
|
|
break;
|
|
} else if (Other->IsCall || isWeakDependency(Other, NI)) {
|
|
Slot = Other->Slot;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If independent of others (or first entry)
|
|
if (Slot == NotFound) Slot = 0;
|
|
|
|
// Find a slot where the needed resources are available
|
|
if (NI->StageBegin != NI->StageEnd)
|
|
Slot = Tally.FindAndReserve(Slot, NI->StageBegin, NI->StageEnd);
|
|
|
|
// Set node slot
|
|
NI->Slot = Slot;
|
|
|
|
// Insert sort based on slot
|
|
j = i;
|
|
for (; 0 < j--;) {
|
|
// Get prior instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
// Should we look further
|
|
if (Slot >= Other->Slot) break;
|
|
// Shuffle other into ordering
|
|
Ordering[j + 1] = Other;
|
|
}
|
|
// Insert node in proper slot
|
|
if (j != i) Ordering[j + 1] = NI;
|
|
}
|
|
}
|
|
|
|
/// Schedule - Order nodes according to selected style.
|
|
///
|
|
void ScheduleDAGSimple::Schedule() {
|
|
// Number the nodes
|
|
NodeCount = std::distance(DAG.allnodes_begin(), DAG.allnodes_end());
|
|
|
|
// Set up minimum info for scheduling
|
|
PrepareNodeInfo();
|
|
// Construct node groups for flagged nodes
|
|
IdentifyGroups();
|
|
|
|
// Test to see if scheduling should occur
|
|
bool ShouldSchedule = NodeCount > 3 && !NoSched;
|
|
// Don't waste time if is only entry and return
|
|
if (ShouldSchedule) {
|
|
// Get latency and resource requirements
|
|
GatherSchedulingInfo();
|
|
} else if (HasGroups) {
|
|
// Make sure all the groups have dominators
|
|
FakeGroupDominators();
|
|
}
|
|
|
|
// Breadth first walk of DAG
|
|
VisitAll();
|
|
|
|
#ifndef NDEBUG
|
|
static unsigned Count = 0;
|
|
Count++;
|
|
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
|
NodeInfo *NI = Ordering[i];
|
|
NI->Preorder = i;
|
|
}
|
|
#endif
|
|
|
|
// Don't waste time if is only entry and return
|
|
if (ShouldSchedule) {
|
|
// Push back long instructions and critical path
|
|
ScheduleBackward();
|
|
|
|
// Pack instructions to maximize resource utilization
|
|
ScheduleForward();
|
|
}
|
|
|
|
DEBUG(printChanges(Count));
|
|
|
|
// Emit in scheduled order
|
|
EmitAll();
|
|
}
|
|
|
|
|
|
/// createSimpleDAGScheduler - This creates a simple two pass instruction
|
|
/// scheduler using instruction itinerary.
|
|
llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAGISel *IS,
|
|
SelectionDAG *DAG,
|
|
MachineBasicBlock *BB) {
|
|
return new ScheduleDAGSimple(false, false, *DAG, BB, DAG->getTarget());
|
|
}
|
|
|
|
/// createNoItinsDAGScheduler - This creates a simple two pass instruction
|
|
/// scheduler without using instruction itinerary.
|
|
llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAGISel *IS,
|
|
SelectionDAG *DAG,
|
|
MachineBasicBlock *BB) {
|
|
return new ScheduleDAGSimple(false, true, *DAG, BB, DAG->getTarget());
|
|
}
|
|
|
|
/// createBFS_DAGScheduler - This creates a simple breadth first instruction
|
|
/// scheduler.
|
|
llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAGISel *IS,
|
|
SelectionDAG *DAG,
|
|
MachineBasicBlock *BB) {
|
|
return new ScheduleDAGSimple(true, false, *DAG, BB, DAG->getTarget());
|
|
}
|