Andrew Lenharth 1f347a318c Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23852 91177308-0d34-0410-b5e6-96231b3b80d8

2005-10-20 23:58:36 +00:00

..

.cvsignore

…

Alpha.h

ret 0; works, not much else

2005-10-20 00:28:31 +00:00

Alpha.td

…

AlphaAsmPrinter.cpp

begining alpha subtarget support

2005-09-29 22:54:56 +00:00

AlphaCodeEmitter.cpp

…

AlphaInstrFormats.td

Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight

2005-10-20 23:58:36 +00:00

AlphaInstrInfo.cpp

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AlphaInstrInfo.h

…

AlphaInstrInfo.td

Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expect new stuff to pass in the JIT tonight

2005-10-20 23:58:36 +00:00

AlphaISelDAGToDAG.cpp

forgot this one

2005-10-20 00:29:02 +00:00

AlphaISelLowering.cpp

This is suppose to work now

2005-10-06 16:54:29 +00:00

AlphaISelLowering.h

ret 0; works, not much else

2005-10-20 00:28:31 +00:00

AlphaISelPattern.cpp

added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh

2005-10-20 19:39:24 +00:00

AlphaJITInfo.cpp

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AlphaJITInfo.h

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AlphaRegisterInfo.cpp

ret 0; works, not much else

2005-10-20 00:28:31 +00:00

AlphaRegisterInfo.h

This seems useful from the original patch that added the function. If there is a reason it is not useful on a RISC type target, let me know and I will pull it out

2005-10-09 20:11:35 +00:00

AlphaRegisterInfo.td

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AlphaRelocations.h

…

AlphaSubtarget.cpp

Sort the cpu and features table, so that the alpha backend doesn't fail EVERY

2005-10-02 07:13:52 +00:00

AlphaSubtarget.h

begining alpha subtarget support

2005-09-29 22:54:56 +00:00

AlphaTargetMachine.cpp

ret 0; works, not much else

2005-10-20 00:28:31 +00:00

AlphaTargetMachine.h

begining alpha subtarget support

2005-09-29 22:54:56 +00:00

Makefile

ret 0; works, not much else

2005-10-20 00:28:31 +00:00