Chris Lattner 95a5e0507e SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits ...

a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36212 91177308-0d34-0410-b5e6-96231b3b80d8

2007-04-17 19:03:21 +00:00

..

CallingConvLower.cpp

add methods for analysis of call results and return nodes.

2007-02-28 07:09:40 +00:00

DAGCombiner.cpp

SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits

2007-04-17 19:03:21 +00:00

LegalizeDAG.cpp

1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.

2007-04-02 21:36:32 +00:00

Makefile

…

ScheduleDAG.cpp

Fix some VC++ warnings.

2007-03-20 20:43:18 +00:00

ScheduleDAGList.cpp

switch the sched unit map over to use a DenseMap instead of std::map. This

2007-02-03 01:34:13 +00:00

ScheduleDAGRRList.cpp

Estimate a cost using the possible number of scratch registers required and use

2007-03-14 22:43:40 +00:00

ScheduleDAGSimple.cpp

Removed tabs everywhere except autogenerated & external files. Add make

2007-04-16 18:10:23 +00:00

SelectionDAG.cpp

fold noop vbitconvert instructions

2007-04-12 05:58:43 +00:00

SelectionDAGISel.cpp

disable switch lowering using shift/and. It still breaks ppc bootstrap for

2007-04-14 19:39:41 +00:00

SelectionDAGPrinter.cpp

Removing even more <iostream> includes.

2006-12-07 20:04:42 +00:00

TargetLowering.cpp

Removed tabs everywhere except autogenerated & external files. Add make

2007-04-16 18:10:23 +00:00