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https://github.com/c64scene-ar/llvm-6502.git
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39aa893201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237481 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.6 KiB
C++
71 lines
2.6 KiB
C++
//===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
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// are used to describe target instructions and their operands.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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using namespace llvm;
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bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
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std::string &Info) const {
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if (ComplexDeprecationInfo)
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return ComplexDeprecationInfo(MI, STI, Info);
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if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
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// FIXME: it would be nice to include the subtarget feature here.
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Info = "deprecated";
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return true;
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}
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return false;
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}
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bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
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const MCRegisterInfo &RI) const {
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if (isBranch() || isCall() || isReturn() || isIndirectBranch())
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return true;
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unsigned PC = RI.getProgramCounter();
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if (PC == 0)
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return false;
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if (hasDefOfPhysReg(MI, PC, RI))
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return true;
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// A variadic instruction may define PC in the variable operand list.
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// There's currently no indication of which entries in a variable
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// list are defs and which are uses. While that's the case, this function
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// needs to assume they're defs in order to be conservatively correct.
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for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
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if (MI.getOperand(i).isReg() &&
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RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
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return true;
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}
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return false;
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}
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bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
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const MCRegisterInfo *MRI) const {
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if (const uint16_t *ImpDefs = ImplicitDefs)
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for (; *ImpDefs; ++ImpDefs)
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if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
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return true;
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return false;
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}
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bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
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const MCRegisterInfo &RI) const {
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for (int i = 0, e = NumDefs; i != e; ++i)
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if (MI.getOperand(i).isReg() &&
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RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
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return true;
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return hasImplicitDefOfPhysReg(Reg, &RI);
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}
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