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https://github.com/c64scene-ar/llvm-6502.git
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2365f51ed0
This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
434 lines
15 KiB
C++
434 lines
15 KiB
C++
//===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Alpha implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "Alpha.h"
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#include "AlphaRegisterInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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using namespace llvm;
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//These describe LDAx
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static const int IMM_LOW = -32768;
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static const int IMM_HIGH = 32767;
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static const int IMM_MULT = 65536;
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static long getUpper16(long l)
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{
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long y = l / IMM_MULT;
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if (l % IMM_MULT > IMM_HIGH)
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++y;
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return y;
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}
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static long getLower16(long l)
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{
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long h = getUpper16(l);
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return l - h * IMM_MULT;
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}
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AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
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: AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
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TII(tii)
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{
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}
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void
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AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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//cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
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// << FrameIdx << "\n";
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//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
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if (RC == Alpha::F4RCRegisterClass)
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BuildMI(MBB, MI, TII.get(Alpha::STS))
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.addReg(SrcReg, false, false, true)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::F8RCRegisterClass)
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BuildMI(MBB, MI, TII.get(Alpha::STT))
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.addReg(SrcReg, false, false, true)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::GPRCRegisterClass)
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BuildMI(MBB, MI, TII.get(Alpha::STQ))
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.addReg(SrcReg, false, false, true)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else
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abort();
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}
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void
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AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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//cerr << "Trying to load " << getPrettyName(DestReg) << " to "
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// << FrameIdx << "\n";
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if (RC == Alpha::F4RCRegisterClass)
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BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::F8RCRegisterClass)
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BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else if (RC == Alpha::GPRCRegisterClass)
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BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
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.addFrameIndex(FrameIdx).addReg(Alpha::F31);
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else
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abort();
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}
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MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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unsigned OpNum,
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int FrameIndex) const {
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// Make sure this is a reg-reg copy.
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unsigned Opc = MI->getOpcode();
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MachineInstr *NewMI = NULL;
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switch(Opc) {
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default:
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break;
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case Alpha::BISr:
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case Alpha::CPYSS:
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case Alpha::CPYST:
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if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
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if (OpNum == 0) { // move -> store
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unsigned InReg = MI->getOperand(1).getReg();
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Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
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((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
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NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
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.addReg(Alpha::F31);
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} else { // load -> move
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unsigned OutReg = MI->getOperand(0).getReg();
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Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
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((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
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NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
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.addReg(Alpha::F31);
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}
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}
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break;
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}
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if (NewMI)
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NewMI->copyKillDeadInfo(MI);
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return 0;
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}
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void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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//cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
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if (RC == Alpha::GPRCRegisterClass) {
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BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == Alpha::F4RCRegisterClass) {
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BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == Alpha::F8RCRegisterClass) {
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BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
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} else {
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cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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}
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void AlphaRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const {
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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static const unsigned CalleeSavedRegs[] = {
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Alpha::R9, Alpha::R10,
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Alpha::R11, Alpha::R12,
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Alpha::R13, Alpha::R14,
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Alpha::F2, Alpha::F3,
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Alpha::F4, Alpha::F5,
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Alpha::F6, Alpha::F7,
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Alpha::F8, Alpha::F9, 0
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};
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return CalleeSavedRegs;
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}
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const TargetRegisterClass* const*
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AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
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&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
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&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
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&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
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};
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return CalleeSavedRegClasses;
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}
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BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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Reserved.set(Alpha::R15);
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Reserved.set(Alpha::R30);
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Reserved.set(Alpha::R31);
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return Reserved;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->hasVarSizedObjects();
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}
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void AlphaRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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// If we have a frame pointer, turn the adjcallstackup instruction into a
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// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
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// <amt>'
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MachineInstr *Old = I;
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uint64_t Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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MachineInstr *New;
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if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
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New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
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.addImm(-Amount).addReg(Alpha::R30);
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} else {
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assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
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New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
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.addImm(Amount).addReg(Alpha::R30);
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}
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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//Alpha has a slightly funny stack:
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//Args
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//<- incoming SP
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//fixed locals (and spills, callee saved, etc)
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//<- FP
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//variable locals
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//<- SP
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void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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bool FP = hasFP(MF);
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Add the base register of R30 (SP) or R15 (FP).
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MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
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// Now add the frame object offset to the offset from the virtual frame index.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
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Offset += MF.getFrameInfo()->getStackSize();
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DOUT << "Corrected Offset " << Offset
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<< " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
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if (Offset > IMM_HIGH || Offset < IMM_LOW) {
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DOUT << "Unconditionally using R28 for evil purposes Offset: "
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<< Offset << "\n";
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//so in this case, we need to use a temporary register, and move the
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//original inst off the SP/FP
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//fix up the old:
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MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
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MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
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//insert the new
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MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
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.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
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MBB.insert(II, nMI);
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} else {
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MI.getOperand(i).ChangeToImmediate(Offset);
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}
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}
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void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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bool FP = hasFP(MF);
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static int curgpdist = 0;
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//handle GOP offset
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BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
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.addGlobalAddress(const_cast<Function*>(MF.getFunction()))
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.addReg(Alpha::R27).addImm(++curgpdist);
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BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
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.addGlobalAddress(const_cast<Function*>(MF.getFunction()))
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.addReg(Alpha::R29).addImm(curgpdist);
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//evil const_cast until MO stuff setup to handle const
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BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
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.addGlobalAddress(const_cast<Function*>(MF.getFunction()));
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// Get the number of bytes to allocate from the FrameInfo
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long NumBytes = MFI->getStackSize();
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if (FP)
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NumBytes += 8; //reserve space for the old FP
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// Do we need to allocate space on the stack?
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if (NumBytes == 0) return;
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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NumBytes = (NumBytes+Align-1)/Align*Align;
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack pointer: r30 -= numbytes
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NumBytes = -NumBytes;
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if (NumBytes >= IMM_LOW) {
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BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
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.addReg(Alpha::R30);
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} else if (getUpper16(NumBytes) >= IMM_LOW) {
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BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
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.addReg(Alpha::R30);
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BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
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.addReg(Alpha::R30);
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} else {
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cerr << "Too big a stack frame at " << NumBytes << "\n";
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abort();
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}
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//now if we need to, save the old FP and set the new
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if (FP)
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{
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BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
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.addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
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//this must be the last instr in the prolog
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BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
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.addReg(Alpha::R30).addReg(Alpha::R30);
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}
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}
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void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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assert(MBBI->getOpcode() == Alpha::RETDAG ||
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MBBI->getOpcode() == Alpha::RETDAGp
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&& "Can only insert epilog into returning blocks");
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bool FP = hasFP(MF);
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// Get the number of bytes allocated from the FrameInfo...
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long NumBytes = MFI->getStackSize();
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//now if we need to, restore the old FP
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if (FP)
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{
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//copy the FP into the SP (discards allocas)
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BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
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.addReg(Alpha::R15);
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//restore the FP
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BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
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}
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if (NumBytes != 0)
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{
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if (NumBytes <= IMM_HIGH) {
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BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
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.addReg(Alpha::R30);
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} else if (getUpper16(NumBytes) <= IMM_HIGH) {
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BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
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.addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
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BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
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.addImm(getLower16(NumBytes)).addReg(Alpha::R30);
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} else {
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cerr << "Too big a stack frame at " << NumBytes << "\n";
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abort();
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}
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}
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}
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unsigned AlphaRegisterInfo::getRARegister() const {
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assert(0 && "What is the return address register");
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return 0;
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}
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unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const {
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return hasFP(MF) ? Alpha::R15 : Alpha::R30;
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}
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unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
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assert(0 && "What is the exception register");
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return 0;
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}
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unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
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assert(0 && "What is the exception handler register");
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return 0;
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}
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#include "AlphaGenRegisterInfo.inc"
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std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
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{
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std::string s(RegisterDescriptors[reg].Name);
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return s;
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}
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